Intel G555 BXC80623G555 ユーザーズマニュアル

Intel

製品コード

BXC80623G555

4

Datasheet, Volume 2

SVID—Subsystem Vendor Identification Register......................................54

SID—Subsystem Identification Register ..................................................54

PXPEPBAR—PCI Express Egress Port Base Address Register.......................55

MCHBAR—Host Memory Mapped Register Range Base Register ..................56

GGC—GMCH Graphics Control Register Register.......................................57

DEVEN—Device Enable Register.............................................................59

PCIEXBAR—PCI Express Register Range Base Address Register..................60

DMIBAR—Root Complex Register Range Base Address Register..................62

PAM0—Programmable Attribute Map 0 Register .......................................63

PAM1—Programmable Attribute Map 1 Register .......................................64

PAM2—Programmable Attribute Map 2 Register .......................................65

PAM3—Programmable Attribute Map 3 Register .......................................66

PAM4—Programmable Attribute Map 4 Register .......................................67

PAM5—Programmable Attribute Map 5 Register .......................................68

PAM6—Programmable Attribute Map 6 Register .......................................69

LAC—Legacy Access Control Register......................................................70

REMAPBASE—Remap Base Address Register............................................74

REMAPLIMIT—Remap Limit Address Register ...........................................74

TOM—Top of Memory Register...............................................................75

TOUUD—Top of Upper Usable DRAM Register ..........................................76

BDSM—Base Data of Stolen Memory Register ..........................................77

BGSM—Base of GTT stolen Memory Register ...........................................77

G Memory Base Register.......................................................................78

TOLUD—Top of Low Usable DRAM Register..............................................79

SKPD—Scratchpad Data Register ...........................................................80

CAPID0_A—Capabilities A Register .........................................................81

PCI Device 1, Function 0–2 Configuration Registers ................................................83
2.6.1

VID1—Vendor Identification Register ......................................................85

DID1—Device Identification Register ......................................................85

PCICMD1—PCI Command Register .........................................................86

PCISTS1—PCI Status Register ...............................................................88

RID1—Revision Identification Register ....................................................90

CC1—Class Code Register .....................................................................90

CL1—Cache Line Size Register...............................................................91

HDR1—Header Type Register ................................................................91

PBUSN1—Primary Bus Number Register..................................................91

SBUSN1—Secondary Bus Number Register..............................................92

SUBUSN1—Subordinate Bus Number Register .........................................92

IOBASE1—I/O Base Address Register .....................................................93

IOLIMIT1—I/O Limit Address Register ....................................................93

SSTS1—Secondary Status Register ........................................................94

MBASE1—Memory Base Address Register................................................95

MLIMIT1—Memory Limit Address Register ...............................................96

PMBASE1—Prefetchable Memory Base Address Register ............................97

PMLIMIT1—Prefetchable Memory Limit Address Register ...........................98

PMBASEU1—Prefetchable Memory Base Address Upper Register.................99

PMLIMITU1—Prefetchable Memory Limit Address Upper Register .............. 100

CAPPTR1—Capabilities Pointer Register................................................. 100

INTRLINE1—Interrupt Line Register ..................................................... 101

INTRPIN1—Interrupt Pin Register......................................................... 101

BCTRL1—Bridge Control Register ......................................................... 102

PM_CAPID1—Power Management Capabilities Register ........................... 104

PM_CS1—Power Management Control/Status Register ............................ 105

SS_CAPID—Subsystem ID and Vendor ID Capabilities Register ................ 106

SS—Subsystem ID and Subsystem Vendor ID Register ........................... 107

MSI_CAPID—Message Signaled Interrupts Capability ID Register ............. 107