Intel i5-3380M AW8063801109500 ユーザーズマニュアル
製品コード
AW8063801109500
Interfaces
28
Datasheet, Volume 1
Note:
Channels A and B can be mapped for physical channel 0 and 1 respectively or vice
versa; however, channel A size must be greater or equal to channel B size.
2.1.3.2.1
Dual-Channel Symmetric Mode
Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously, since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
performance on real world applications. Addresses are ping-ponged between the
channels after each cache line (64-byte boundary). If there are two requests, and the
second request is to an address on the opposite channel from the first, that request can
be sent before data from the first request has returned. If two consecutive cache lines
are requested, both may be retrieved simultaneously, since they are ensured to be on
opposite channels. Use Dual-Channel Symmetric mode when both Channel A and
Channel B DIMM connectors are populated in any order, with the total amount of
memory in each channel being the same.
When both channels are populated with the same memory capacity and the boundary
between the dual channel zone and the single channel zone is the top of memory, the
IMC operates completely in Dual-Channel Symmetric mode.
between the dual channel zone and the single channel zone is the top of memory, the
IMC operates completely in Dual-Channel Symmetric mode.
Note:
The DRAM device technology and width may vary from one channel to the other.
2.1.4
Rules for Populating Memory Slots
In all System Memory Organization Modes, the frequency and latency timings of the
system memory is the lowest supported frequency and slowest supported latency
timings of all memory DIMM modules placed in the system, as determined through the
SPD registers.
system memory is the lowest supported frequency and slowest supported latency
timings of all memory DIMM modules placed in the system, as determined through the
SPD registers.
Figure 2-1. Intel
®
Flex Memory Technology Operation
C H B
C H A
B
B
C
B
B
C
N o n in t e r le a v e d
a c c e s s
a c c e s s
D u a l c h a n n e l
in t e r le a v e d a c c e s s
in t e r le a v e d a c c e s s
T O M
C H A a n d C H B c a n b e c o n fig u r e d to b e p h y s ic a l c h a n n e ls 0 o r 1
B – T h e la r g e s t p h y s ic a l m e m o r y a m o u n t o f th e s m a lle r s iz e m e m o r y m o d u le
C – T h e r e m a in in g p h y s ic a l m e m o r y a m o u n t o f th e la r g e r s iz e m e m o r y m o d u le
B – T h e la r g e s t p h y s ic a l m e m o r y a m o u n t o f th e s m a lle r s iz e m e m o r y m o d u le
C – T h e r e m a in in g p h y s ic a l m e m o r y a m o u n t o f th e la r g e r s iz e m e m o r y m o d u le