Intel G1620T CM8063701448300 ユーザーズマニュアル
![Intel](https://files.manualsbrain.com/attachments/5a71b1e7f60391972dadeef20435931cbf4621a5/common/fit/150/50/86c99b5f14aeb2708e9a9e1b5305af4ccf882c1af0155dad25413c2ed84e/brand_logo.png)
製品コード
CM8063701448300
Datasheet
1073
PCU - Serial Peripheral Interface (SPI)
20.4.45
BCR (BIOS_Control_Register_bios)—Offset FCh
BIOS control register. This register formerly was in the 0:31:0 config space
Access Method
Default: 00000020h
6
0b
RW/1C
SMI WPD Status (SMIWPST): Set when SMI is generated upon trying to set WPD
from a 1'b0 to a 1'b1 by not SMM code (while LE and SMIWPEN are set). Write a 1'b1 to
this bit should clear it and clear the SMI (send DEASSERT_SMI)
5:0
0b
RO
RSVD1: Reserved
Bit
Range
Default &
Access
Description
Type: Memory Mapped I/O Register
(Size: 32 bits)
BIOS_Control_Register_bios: [SPI_BASE_ADDRESS] + FCh
SPI_BASE_ADDRESS Type: PCI Configuration Register (Size: 32
bits)
SPI_BASE_ADDRESS Reference: [B:0, D:31, F:0] + 54h
SPI_BASE_ADDRESS Reference: [B:0, D:31, F:0] + 54h
31
28
24
20
16
12
8
4
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
RS
VD0
EIS
S
RS
VD1
SRC
LE
WPD
Bit
Range
Default &
Access
Description
31:6
0b
RO
RSVD0: Reserved
5
1b
RW/L
Enable InSMM_STS (EISS): When this bit is set, the BIOS region is writable only to
SMM code. Today BIOS Flash is writable if WPD is a '1'. If this bit [lb]5[rb] is set, then
WPD must be a 1'b1 and iosfep_xxx_hprot[lb]1[rb] signal be 1'b1 also. If this bit
[lb]5[rb] is clear, then BIOS is writable based only on WPD = 1'b1 and the
iosfep_xxx_hprot[lb]1[rb] signal is a don't care.
4
0b
RO
RSVD1: Reserved
3:2
00b
RW
SPI Read Configuration (SRC): This 2-bit field controls two policies related to BIOS
reads on the SPI interface: Bit 3 - Prefetch Enable, Bit 2 - Cache Disable. Settings are
summarized below: '00' : No prefetching, but caching enabled. Direct Memory reads
load the read buffer cache with 'valid' data, allowing repeated reads to the same range
to complete quickly. '01' : No prefetching and no caching. One-to-one correspondence
of host BIOS reads to SPI cycles. This value can be used to invalidate the cache. '10' :
Prefetching and Caching enabled. This mode is used for long sequences of short reads to
consecutive addresses (i.e. shadowing) '11' : Illegal. Caching must be enabled when
Prefetching is enabled. This eliminates the need for a complex prefetch-flushing
mechanism. Note that if BIOS direct read caching is disabled while data has already
been cached internally, subsequent BIOS direct reads will continue to return data from
the cache until the cache is invalidated.
1
0b
RW/L
Lock Enable (LE): When set, WPD bit could be set from a 1'b0 to a 1'b1 only by SMM
code. When cleared, setting the WP bit is allowed in all modes and SMI is not generated.
Once set, this bit can only be cleared by a PLTRST#. When this bit is set, EISS - bit
[lb]5[rb] of this register is locked down.