Intel E7-8891 v2 CM8063601377422 ユーザーズマニュアル
製品コード
CM8063601377422
Processor Uncore Configuration Registers
118
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.2.12 LEAKY_BUCKET_CNTR_LO
11:6
RW
0x0
LEAKY_BKT_CFG_HI (leaky_bkt_cfg_hi):
This is the higher order bit select mask of the two hot encoding threshold.
The value of this field specify the bit position of the mask:
00h: reserved
01h: LEAKY_BUCKET_CNTR_LO bit 1, i.e. bit 12 of the full 53b counter
...
1Fh: LEAKY_BUCKET_CNTR_LO bit 31, i.e. bit 42 of the full 53b counter
20h: LEAKY_BUCKET_CNTR_HI bit 0, i.e. bit 43 of the full 53b counter
...
29h: LEAKY_BUCKET_CNTR_HI bit 9, i.e. bit 52 of the full 53b counter
2Ah - 3F: reserved
00h: reserved
01h: LEAKY_BUCKET_CNTR_LO bit 1, i.e. bit 12 of the full 53b counter
...
1Fh: LEAKY_BUCKET_CNTR_LO bit 31, i.e. bit 42 of the full 53b counter
20h: LEAKY_BUCKET_CNTR_HI bit 0, i.e. bit 43 of the full 53b counter
...
29h: LEAKY_BUCKET_CNTR_HI bit 9, i.e. bit 52 of the full 53b counter
2Ah - 3F: reserved
MRC BIOS must program this register to any nonzero value before switching
to NORMAL mode.
5:0
RW
0x0
LEAKY_BKT_CFG_LO (leaky_bkt_cfg_lo):
This is the lower order bit select mask of the two hot encoding threshold.
The value of this field specify the bit position of the mask:
00h: reserved
01h: LEAKY_BUCKET_CNTR_LO bit 1, i.e. bit 12 of the full 53b counter
...
1Fh: LEAKY_BUCKET_CNTR_LO bit 31, i.e. bit 42 of the full 53b counter
20h: LEAKY_BUCKET_CNTR_HI bit 0, i.e. bit 43 of the full 53b counter
...
29h: LEAKY_BUCKET_CNTR_HI bit 9, i.e. bit 52 of the full 53b counter
2Ah - 3F: reserved
00h: reserved
01h: LEAKY_BUCKET_CNTR_LO bit 1, i.e. bit 12 of the full 53b counter
...
1Fh: LEAKY_BUCKET_CNTR_LO bit 31, i.e. bit 42 of the full 53b counter
20h: LEAKY_BUCKET_CNTR_HI bit 0, i.e. bit 43 of the full 53b counter
...
29h: LEAKY_BUCKET_CNTR_HI bit 9, i.e. bit 52 of the full 53b counter
2Ah - 3F: reserved
MRC BIOS must program this register to any nonzero value before switching
to NORMAL mode.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
1
Bus:
1
Device: 29
Function:
1
Offset:
0xc0
Bit
Attr
Default
Description
31:0
RW_V
0x0
Leaky Bucket Counter Low (leaky_bkt_cntr_lo):
This is the lower 32-bit of the leaky bucket counter. The full counter is
actually a 53b “DCLK” counter. There is a least significant 11b of the 53b
counter is not captured in CSR. The carry “strobe” from the not-shown least
significant 11b counter will trigger this 42b counter pair to count. The 42b
counter-pair is compared with the two-hot encoding threshold specified by
the LEAKY_BUCKET_CFG_HI and LEAKY_BUCKET_CFG_LO pair. When the
counter bits specified by the LEAKY_BUCKET_CFG_HI and
LEAKY_BUCKET_CFG_LO are both set, the 53b counter is reset and the
leaky bucket logic will generate a LEAK strobe last for 1 DCLK.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
1
Bus:
1
Device: 29
Function:
1
Offset:
0xb8
Bit
Attr
Default
Description