Intel E7-8891 v2 CM8063601377422 ユーザーズマニュアル

20

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

MLC

Mid Level Cache

NCTF

Non-Critical to Function: NCTF locations are typically redundant ground or non-

critical reserved, so the loss of the solder joint continuity at end of life conditions 

will not affect the overall product functionality.

NEBS

Network Equipment Building System. NEBS is the most common set of 

environmental design guidelines applied to telecommunications equipment in the 

United States.

PCH

Platform Controller Hub. The next generation chipset with centralized platform 

capabilities including the main I/O interfaces along with display connectivity, 

audio features, power management, manageability, security and storage 

features.

PCU

Power Control Unit.

PCI Express 3.0

The third generation PCI Express specification that operates at 8 GT/s data 

transfer rate per lane per direction. PCI Express 3.0 is completely backward 

compatible with PCI Express 1.0 and 2.0.

PCI Express

PCI Express Generation 2.0/3.0

PCI Express 2.0

PCI Express Generation 2.0

PECI

Platform Environment Control Interface

Phit

Physical Unit. Data transfer unit of Intel

®

 QPI Physical Layer. 1 Phit is equal to18 

bits in ‘full width mode’ and 9 bits in ‘half width mode’.

Processor

The 64-bit, single-core or multi-core component (package)

Processor Core

A processing and execution unit which has an instruction cache, data cache, and 

256-KB L2 cache. All processor cores share the LLC.

R3QPI

Ring to Intel

®

 QPI agent interface. An internal logic block providing interface 

between internal Ring and Intel

®

 QPI Agents.

Rank

A unit of DRAM corresponding four to eight devices in parallel, ignoring ECC. 

These devices are usually, but not always, mounted on a single side of a DDR3 

DIMM.

RDIMM

Registered Dual In-line Memory Module

Scalable

Intel Xeon processor E7 v2 product family-platform targeted for scalable designs 

using third party Node Controller chip. In these designs, Node Controller is used 

to scale the design beyond one/two/four sockets.

SCI

System Control Interrupt. Used in ACPI protocol.

Server SKU

A processor Stock Keeping Unit (SKU) to be installed in either server or 

workstation platforms. Electrical, power and thermal specifications for these 

SKU’s are based on specific use condition assumptions. Server processors may 

be further categorized as Efficient Performance server, workstation and HPC 

SKUs. For further details on use condition assumptions, please refer to the latest 

Product Release Qualification (PRQ) Report available via your Customer Quality 

Engineer (CQE) contact.

SMBus

System Management Bus. A two-wire interface through which simple system and 

power management related devices can communicate with the rest of the 

system. It is based on the principals of the operation of the I

2

C* two-wire serial 

bus from Philips Semiconductor.

Storage Conditions

A non-operational state. The processor may be installed in a platform, in a tray, 

or loose. Processors may be sealed in packaging or exposed to free air. Under 

these conditions, processor landings should not be connected to any supply 

voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” 

(that is, unsealed packaging or a device removed from packaging material) the 

processor must be handled in accordance with moisture sensitivity labeling 

(MSL) as indicated on the packaging material.

TAC

Thermal Averaging Constant

TDP

Thermal Design Power

TSOD

Temperature Sensor On DIMM