Intel E7-8891 v2 CM8063601377422 ユーザーズマニュアル

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

263

Datasheet Volume Two: Functional Description, February 2014

MISC Control and Status Register 1.

4:4

RW

0x0

enable_system_error_only_for_aer:

Applies only to root ports. For Dev#0 in DMI mode, this bit 

is to be left at default value always.When this bit is set, the 

PCI Express errors do not trigger an MSI or Intx interrupt, 

regardless of the whether MSI or INTx is enabled or not. 

Whether or not PCI Express errors result in a system event 

like NMI/SMI/PMI/CPEI is dependent on whether the 

appropriate system error or override system error enable 

bits are set or not.
See section titled PCI Express Error Reporting Specifics in 

the RAS chapter for details of how this bit interacts with 

other control bits in signalling errors to the IIO global error 

reporting logic.
When this bit is clear, PCI Express errors are reported via 

MSI or INTx and/or NMI/SMI/MCA/CPEI. When this bit is 

clear, and ‘System Error on Fatal Error Enable’ bit in 

ROOTCON register is set, then NMI/SMI/MCA is (also) 

generated for a PCI Express fatal error. Similar behavior for 

nonfatal and corrected errors.

3:3

RW

0x0

enable_acpi_mode_for_hotplug:

2:2

RW

0x0

enable_acpi_mode_for_pm:

1:1

RW_O

0x0

inbound_configuration_enable:

0:0

RV

-

Reserved.

31:20

RV

-

Reserved.

19:19

RW

0x1

vcm_arb_in_vc1:

Only available for Device 0 Function 0.

18:18

RW

0x0

no_vcm_throttle_in_quiesce:

Only available for Device 0 Function 0

17:17

RW1CS

0x0

locked_read_timed_out:

Indicates that a locked read request incurred a completion timeout on PCI 

Express/DMI

16:16

RW1C

0x0

received_pme_to_ack:

Indicates that IIO received a PME turn off ack packet or it timed out waiting 

for the packet

15:10

RV

-

Reserved.