Intel E7-8891 v2 CM8063601377422 ユーザーズマニュアル

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

357

Datasheet Volume Two: Functional Description, February 2014

5:5

RO

0x0

vga_palette_snoop_enable:

Not applicable to internal devices. Hardwired to 0.

4:4

RO

0x0

memory_write_and_invalidate_enable:

Not applicable to internal devices. Hardwired to 0.

3:3

RO

0x0

special_cycle_enable:

Not applicable. Hardwired to 0.

2:2

RO

0x0

bus_master_enable:

Hardwired to 0 since these devices don’t generate any transactions

1:1

RO

0x0

memory_space_enable:

Hardwired to 0 since these devices don’t decode any memory BARs

0:0

RO

0x0

io_space_enable:

Hardwired to 0 since these devices don’t decode any I/O BARs

15:15

RO

0x0

detected_parity_error:

This bit is set when the device receives a packet on the primary side with an 

uncorrectable data error (including a packet with poison bit set) or an 

uncorrectable address/control parity error. The setting of this bit is 

regardless of the Parity Error Response bit (PERRE) in the PCICMD register. 

R2PCIe will never set this bit.

14:14

RO

0x0

signaled_system_error:

Hardwired to 0

13:13

RO

0x0

received_master_abort:

Hardwired to 0

12:12

RO

0x0

received_target_abort:

Hardwired to 0

11:11

RO

0x0

signaled_target_abort:

Hardwired to 0

10:9

RO

0x0

devsel_timing:

Not applicable to PCI Express. Hardwired to 0.