Intel E7-8891 v2 CM8063601377422 ユーザーズマニュアル

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CM8063601377422
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Integrated I/O (IIO) Configuration Registers
370
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
Type:
CFG
PortID:
N/A
Bus:
0
Device:
5Function:0
Offset:
0x140
Bit
Attr
Default
Description
31:31
RW
0x0
flushpendwr:
Whenever this bit is written to 1 (regardless what the current value of this bit 
is), IRP block first clears bit 0 in CIPSTS register and takes a snapshot of the 
currently pending write transactions to dram in Write Cache, wait for them to 
complete fully (that is, deallocate the corresponding Write Cache/RRB entry) 
and then set bit 0 in CIPSTS register.
30:30
RW
0x0
adr_snapshot_req:
Whenever this bit is written to 1, this implies wr$ snapshot request was due 
to ADR. This is a status indication and does not cause the snapshot to occur.
29:29
RV
-
Reserved.
28:28
RW
0x0
diswrupdtflow:
When set, PCIWriteUpdate command is never issued on IDI and the writes 
that triggered this flow would be treated as “normal” writes and the rules 
corresponding to the “normal writes” apply.
27:17
RV
-
Reserved.
16:16
RW
0x0
rrbsize_3:
This is the MSB bit for the rrbsize. The lower 3-bits of the rrbsize reside in 
CIPCTRL[11:9]
15:15
RW
0x0
rd_merge_enable:
14:12
RW
0x0
socketid:
This is the BIOS programmed field that indicates the “SocketID” of this 
particular socket. “SocketID” is the unique value that each socket in the 
system gets for DCA/DIO target determination. Normally this value is the 
same as the APICID[7:5] of the cores in the socket, but it can be other 
values as well, if system topology were to not allow that straight mapping.
IIO uses strapped NodeID to compare against the target NodeID determined 
by using the target SocketID value as a lookup into the CIPDCASAD register. 
If there is a match, then a PCIDCAHint is not sent (since the data is already 
located in the same LLC).
This register is not used for this comparison. It is not used by hardware at 
all.