Intel E7-8891 v2 CM8063601377422 ユーザーズマニュアル

388

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

LT DMA Protected Range.

General Description: This register holds the address and size of the DMA protected 
memory region for LT-SX MP usage.

0:0

RW_LB

0x0

enable_isa_hole:

When this bit is set, inbound DMA accesses to the ISA Hole region are 

aborted by IIO. If clear, inbound DMA accesses to the ISA hole region are 

forwarded to dram. Refer to the Address Map chapter for more details.

The ISA Hole is no longer supported by Intel Xeon processor E7-

2800/4800/8800 v2 product family Product Family (ISA segment exists but 

the feature is defeatured). This bit must never be set.

31:20

RO_V

0x0

topofdpr:

Top address + 1 of DPR. This is RO, and it is copied by HW from 

TSEGBASE[31:20].

19:12

RV

-

Reserved.

11:4

RW_L

0x0

size:

This is the size of memory, in MB, that will be protected from DMA accesses. 

A value of 0x00 in this field means no additional memory is protected. The 

maximum amount of memory that will be protected is 255 MB.

The amount of memory reported in this field will be protected from all DMA 

accesses. The top of the protected range is typically the BASE of TSEG -1. 

BIOS is expected to program that in to bits 31:20 of this register.

Notes:
If TSEG is not enabled, then the top of this range becomes the base ME 

stolen space, whichever would have been the location of TSEG, assuming it 

had been enabled.
The DPR range works independently of any other range - Generic Protected 

ranges, TSEG range, Intel

®

VT-d tables, Intel

®

VT-d protection ranges, 

MMCFG protection range and is done post any Intel

®

VT-d translation or LT 

checks. Therefore incoming cycles are checked against this range after the 

Intel

®

VT-d translation and faulted if they hit this protected range, even if 

they passed the Intel

®

VT-d translation.

All the memory checks are ORed with respect to NOT being allowed to go to 

memory. So if either Generic protection range, DPR, Intel

®

VT-d, TSEG 

range disallows the cycle, then the cycle is not allowed to go to memory. Or 

in other words, all the above checks must pass before a cycle is allowed to 

DRAM.
DMA remap engines are allowed to access the DPR region without any 

faulting. It is always legal for any DMA remap engine to read or write into 

the DPR region, thus DMA remap accesses must not be checked against the 

DPR range.

3:3

RV

-

Reserved.