Intel E7-8891 v2 CM8063601377422 ユーザーズマニュアル

418

Intel

®

 Xeon

® 

Processor E7-2800/4800/8800 v2 Product Family

Datasheet Volume Two: Functional Description, February 2014

Intel

®

VT-d IOTLB Invalidate.

6:6

RW

0x0

ih:

Invalidation Hint.
The field provides hint to hardware to preserve or flush the respective non-

leaf page-table entries that may be cached in hardware.0: Software may 

have modified both leaf and non-leaf page-table entries corresponding to 

mappings specified in the ADDR and AM fields. On a page-selective 

invalidation request, IIO must flush both the cached leaf and nonleaf page-

table entries corresponding to mappings specified by ADDR and AM fields. 

IIO performs a domain-level invalidation on non-leaf entries and page-

selective-domain-level invalidation at the leaf level
1: Software has not modified any non-leaf page-table entries corresponding 

to mappings specified in the ADDR and AM fields. On a page-selective 

invalidation request, IIO preserves the cached non-leaf page-table entries 

corresponding to mappings specified by ADDR and AM fields and performs 

only a page-selective invalidation at the leaf level 

5:0

RW

0x0

am:

Address Mask.
IIO supports values of 0-9. All other values result in undefined results.

63:63

RW_V

0x0

ivt:

Invalidate IOTLB cache
Software requests IOTLB invalidation by setting this field. Software must 

also set the requested invalidation granularity by programming the IIRG 

field.Hardware clears the Intel

®

VT field to indicate the invalidation request 

is complete. Hardware also indicates the granularity at which the 

invalidation operation was performed through the IAIG field. Software must 

read back and check the CPU field to be clear to confirm the invalidation is 

complete.
When CPU field is set, software must not update the contents of this register 

(and Invalidate Address register, if it is being used), nor submit new IOTLB 

invalidation requests. 

62:62

RV

-

rsz2:

Reserved.