Intel E7-8891 v2 CM8063601377422 ユーザーズマニュアル
製品コード
CM8063601377422
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
71
Datasheet Volume Two: Functional Description, February 2014
Registers Overview and Configuration Process
12
Registers Overview and
Configuration Process
This volume of the Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family
Datasheet documents a part of the Configuration Status Registers (CSRs) of each
individual functional block in the uncore logic. Refer to Intel® Xeon® Processor E7-
2800/4800/8800 v2 Product Family External Design Specification (EDS) for a complete
CSRs.
Datasheet documents a part of the Configuration Status Registers (CSRs) of each
individual functional block in the uncore logic. Refer to Intel® Xeon® Processor E7-
2800/4800/8800 v2 Product Family External Design Specification (EDS) for a complete
CSRs.
The Intel® Xeon® Processor E7-2800/4800/8800 v2 Product Family contains one or
more PCI devices within each individual functional block. The configuration registers for
these devices are mapped as devices residing on the PCI Bus assigned for the
processor socket. CSRs are the basic hardware elements that configure the uncore logic
to support various system topologies, memory configuration and densities, and all the
hardware hooks required for RAS operations. For the complete
more PCI devices within each individual functional block. The configuration registers for
these devices are mapped as devices residing on the PCI Bus assigned for the
processor socket. CSRs are the basic hardware elements that configure the uncore logic
to support various system topologies, memory configuration and densities, and all the
hardware hooks required for RAS operations. For the complete
12.1
Platform Configuration Structure
The DMI2 physically connects the processor and the PCH. From a configuration
standpoint the DMI2 is a logical extension of PCI Bus 0. DMI2 and the internal devices
in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software.
As a result,
standpoint the DMI2 is a logical extension of PCI Bus 0. DMI2 and the internal devices
in the processor IIO and PCH logically constitute PCI Bus 0 to configuration software.
As a result,
all devices internal to the processor
IIO and the PCH appear to be on PCI
Bus 0.
12.1.1
Processor IIO Devices (CPUBUSNO (0))
The processor IIO contains 10 PCI devices within a single, physical component. The
configuration registers for the devices are mapped as devices residing on PCI Bus
“CPUBUSNO(0) ” where CPUBUSNO(0) is programmable by BIOS.
configuration registers for the devices are mapped as devices residing on PCI Bus
“CPUBUSNO(0) ” where CPUBUSNO(0) is programmable by BIOS.