Intel E7-4850 v2 CM8063601272906 ユーザーズマニュアル
製品コード
CM8063601272906
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
155
Datasheet Volume Two: Functional Description, February 2014
Processor Uncore Configuration Registers
For lock-step channel configuration, only one x8 device can be tagged per rank-pair.
SMM software must copy the faildevice log from Channel 0/2 to the corresponding
register in Channel 1/3, then set EN for both channels in lockstepped pair.
SMM software must copy the faildevice log from Channel 0/2 to the corresponding
register in Channel 1/3, then set EN for both channels in lockstepped pair.
There is no hardware logic to report incorrect programming error. Unpredictable error
and / or silent data corruption will be the consequence of such programming error.
and / or silent data corruption will be the consequence of such programming error.
If the rank-sparing is enabled, it is recommended to prioritize the rank-sparing before
triggering the device tagging due to the nature of the device tagging would drop the
correction capability and any subsequent ECC error from this rank would cause
uncorrectable error.
triggering the device tagging due to the nature of the device tagging would drop the
correction capability and any subsequent ECC error from this rank would cause
uncorrectable error.
13.3
Home Agent Registers
The Home Agent is responsible for memory transactions and interacts with the
processor’s ring and handles incoming and outgoing transactions.
processor’s ring and handles incoming and outgoing transactions.
Type:
CFG
PortID: N/A
Bus:
1
Device: 16
Function:
2,3,6,7
Bus:
1
Device: 30
Function:
2,3,6,7
Offset:
0x140, 0x141 , 0x142 , 0x143, 0x144, 0x145, 0x146, 0x147
Bit
Attr
Default
Description
7:7
RWS_LB
0x0
Device tagging enable for this rank (en):
Device tagging (SDDC) enable for this rank. Once set, the parity device of
the rank is used for the replacement device content. After tagging, the rank
will no longer have the “correction” capability. ECC error “detection”
capability will not degrade after setting this bit.
Warning: For DDR3 lock-step channel configuration, only one x8 device can
Warning: For DDR3 lock-step channel configuration, only one x8 device can
be tagged per rank-pair. SMM software must copy the faildevice log from
Channel 0/2 to the corresponding register in Channel 1/3, then set EN for
both channels in lockstepped pair.
Must never be enable prior using IOSAV
DDDC:
On DDDC supported systems, BIOS has the option to enable SDDC in
Must never be enable prior using IOSAV
DDDC:
On DDDC supported systems, BIOS has the option to enable SDDC in
conjunction with DDDC_CNTL:SPARING to enable faster sparing with SDDC
substitution. This field is cleared by HW on completion of DDDC sparing.
6:6
RV
-
Reserved.
5:0
RWS_V
0x3f
Fail Device ID for this rank (faildevice):
Hardware will capture the fail device ID of the rank in the FailDevice field
upon successful correction from the device correction engine. After SDDC is
enabled HW may not update this field.
In DDR3 lockstep mode, the faildevice will only be logged by hardware on
In DDR3 lockstep mode, the faildevice will only be logged by hardware on
Channel 0/2 of lockstepped pair. SMM must copy faildevice to the other
lockstepped channel before enabling SDDC.
Native DDR/VMSE2:1/VMSE1:1x8:
Valid Range is decimal 0-17 to indicate which x4 device (independent
Valid Range is decimal 0-17 to indicate which x4 device (independent
channel) or x8 device (lock-step mode) has failed.
VMSE1:1x4 (DDDC):
Valid Range is decimal 0-35 to indicate which x4 device has failed.
Valid Range is decimal 0-35 to indicate which x4 device has failed.
Note that when DDDC has been enabled on the nonspare device, and a
subsequent failure of the spare device occurs, the value logged here will be
equal to the DDDC faildevice.
Since the device tagging should not be enabled at first boot, the default
Since the device tagging should not be enabled at first boot, the default
value in this field is chosen to be out of the range.