Intel E7-8890 v2 CM8063601213513 ユーザーズマニュアル
製品コード
CM8063601213513
Intel
®
Xeon
®
Processor E7-2800/4800/8800 v2 Product Family
69
Datasheet Volume Two: Functional Description, February 2014
Performance Monitoring
11
Performance Monitoring
This chapter will provide an overview of the Intel Xeon processor E7 v2 product family
performance monitoring (perfmon) features and describe how the architecture works at
a high level.
performance monitoring (perfmon) features and describe how the architecture works at
a high level.
11.1
Terminology
• UNIT: A UNIT means any non IA-Core unit supporting PerfMon including: Cbos,
Home Agent (HA), Memory Controller (iMC), Intel QPI Agent, Ubox, and PCU.
• PMI: Performance Monitoring Interrupt - triggered by counter overflows and used
to cause PerfMon counters in selected cores to stall and to trigger software
interrupt handlers to process the information stores in the perfmons.
interrupt handlers to process the information stores in the perfmons.
• Counter: A counter is a physical register inside of the uncore that can be
programmed to count a specific “event.”
• Event: An event is what you program a counter to count. For example, one might
program a “counter” to count the “LLC hits” event.
11.2
Infrastructure
The Intel Xeon processor E7 v2 product family uncore performance monitor utilizes a
distributed design. There are essential PerfMon counter blocks stamped throughout the
uncore which have numerous event signals fed into them and control logic to select
which events to count and how to count.
distributed design. There are essential PerfMon counter blocks stamped throughout the
uncore which have numerous event signals fed into them and control logic to select
which events to count and how to count.
There are two global Registers that exist inside of the counter reporting agent. The
“Global Control” Register controls how the Uncore Perfmon behaves at a global level.
The “Global Status” CR provides information about the status of the system.
“Global Control” Register controls how the Uncore Perfmon behaves at a global level.
The “Global Status” CR provides information about the status of the system.
Each unit has a single “Unit Control Register” that can be used to perform global
operations across the unit such as freezing and resetting the counters. They will also
have a “Unit Status” register that provides information about which register
overflowed.
operations across the unit such as freezing and resetting the counters. They will also
have a “Unit Status” register that provides information about which register
overflowed.
Some units have a separate special control register that allow for special event
filtering/control within the unit.
filtering/control within the unit.
11.3
PCU PerfMon
11.3.1
High-Level Overview
Perfmon for the PCU is very similar to the standard uncore perfmon used throughout
the Intel Xeon processor E7 v2 product family uncore. The PCU perfmon has some
adaptations from the standard uncore perfmon to enable some special usage models
and to push some of the complexity out of the hardware and into PCU microcode.
the Intel Xeon processor E7 v2 product family uncore. The PCU perfmon has some
adaptations from the standard uncore perfmon to enable some special usage models
and to push some of the complexity out of the hardware and into PCU microcode.
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