Intel J1750 FH8065301562600 ユーザーズマニュアル
製品コード
FH8065301562600
PCU – Universal Asynchronous Receiver/Transmitter (UART)
1076
Datasheet
21.2
Features
The serial port consists of a UART which supports a subset of the functions of the 16550
industry standard.
industry standard.
The UART performs serial-to-parallel conversion on data characters received from a
peripheral device and parallel-to-serial conversion on data characters received from the
processor. The processor may read the complete status of the UART at any time during
the functional operation. Available status information includes the type and condition of
the transfer operations being performed by the UART and any error conditions.
peripheral device and parallel-to-serial conversion on data characters received from the
processor. The processor may read the complete status of the UART at any time during
the functional operation. Available status information includes the type and condition of
the transfer operations being performed by the UART and any error conditions.
The serial port may operate in either FIFO or non-FIFO mode. In FIFO mode, a 16-byte
transmit FIFO holds data from the processor to be transmitted on the serial link and a
16-byte Receive FIFO buffers data from the serial link until read by the processor.
transmit FIFO holds data from the processor to be transmitted on the serial link and a
16-byte Receive FIFO buffers data from the serial link until read by the processor.
The UART includes a programmable baud rate generator which is capable of generating
a baud rate of between 50 bps and 115,200 bps from a fixed baud clock input of
1.8432 MHz. The baud rate is calculated as follows:
a baud rate of between 50 bps and 115,200 bps from a fixed baud clock input of
1.8432 MHz. The baud rate is calculated as follows:
Baud Rate Calculation:
The divisor is defined by the Divisor Latch LSB and Divisor Latch MSB registers. Some
common values are shown in
common values are shown in
The UART has interrupt support and those interrupts may be programmed to the user's
requirements, minimizing the computing required to handle the communications link.
Each UART may operate in a polled or an interrupt driven environment as configured by
software.
requirements, minimizing the computing required to handle the communications link.
Each UART may operate in a polled or an interrupt driven environment as configured by
software.
BaudRate
1.8432
6
10
16 Divisor
-----------------------
=
Table 156. Baud Rate Examples
Desired Baud Rate
Divisor
Divisor Latch LSB
Register
Divisor Latch MSB
Register
115,200
1
1h
0h
57,600
2
2h
0h
38,400
3
3h
0h
19,200
6
6h
0h
9,600
12
Ch
0h
4,800
24
18h
0h
2,400
48
30h
0h
1,200
96
60h
0h
300
384
80h
1h
50
2,304
0h
9h