Acer Intel Celeron G530 KC.53001.CDG ユーザーズマニュアル

78

 Datasheet

SLP#

Input

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter 
the Sleep state. During Sleep state, the processor stops providing internal clock 
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. 
Processors in this state will not recognize snoops or interrupts. The processor 
will only recognize the assertion of the RESET# signal, deassertion of SLP#, and 
removal of the BCLK input while in Sleep state. If SLP# is deasserted, the 
processor exits Sleep state and returns to Stop-Grant state, restarting its internal 
clock signals to the bus and processor core units. 

SMI#

Input

SMI# (System Management Interrupt) is asserted asynchronously by system 
logic. On accepting a System Management Interrupt, the processor saves the 
current state and enters System Management Mode (SMM). An SMI 
Acknowledge transaction is issued, and the processor begins program execution 
from the SMM handler.

If SMI# is asserted during the deassertion of RESET#, the processor will tristate 
its outputs.

STPCLK#

Input

Assertion of STPCLK# (Stop Clock) causes the processor to enter a low power 
Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction 
and stops providing internal clock signals to all processor core units except the 
system bus and APIC units. The processor continues to snoop bus transactions 
and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, 
the processor restarts its internal clock to all units and resumes execution. The 
assertion of STPCLK# has no effect on the bus clock; STPCLK# is an 
asynchronous input.

TCK

Input

TCK (Test Clock) provides the clock input for the processor Test Bus (also known 
as the Test Access Port).

TDI

Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides the 
serial input needed for JTAG specification support.

TDO

Output

TDO (Test Data Out) transfers serial test data out of the processor. TDO provides 
the serial output needed for JTAG specification support.

TESTHI[12:8]

TESTHI[5:0]

Input

TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC power source 
through a resistor for proper processor operation. See 

 for more 

details.

THERMDA

Other

Thermal Diode Anode. See 

THERMDC

Other

Thermal Diode Cathode. See 

THERMTRIP#

Output

Assertion of THERMTRIP# (Thermal Trip) indicates that the processor junction 
temperature has reached a level where permanent silicon damage may occur. 
Measurement of the temperature is accomplished through an internal thermal 
sensor that is configured to trip at approximately 135 

°C. Upon assertion of 

THERMTRIP#, the processor will shut off its internal clocks (thus halting program 
execution) in an attempt to reduce the processor junction temperature. To protect 
the processor, its core voltage (VCC) must be removed following the assertion of 
THERMTRIP#. See 

 for the appropriate power down 

sequence and timing requirements. 

For processors with CPUID of 0xF27 and beyond:

•

Driving of the THERMTRIP# signal is enabled within 10 

µ

s of the assertion 

of PWRGOOD, and is disabled on de-assertion of PWRGOOD. Once 
activated, THERMTRIP# remains latched until PWRGOOD is de-asserted. 
While the de-assertion of the PWRGOOD signal will de-assert 
THERMTRIP#, if the processor’s junction temperature remains at or above 
the trip level, THERMTRIP# will again be asserted within 10 

µ

s of the 

assertion of PWRGOOD.

TMS

Input

TMS (Test Mode Select) is a JTAG specification support signal used by debug 
tools.

TRDY#

Input

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to 
receive a write or implicit writeback data transfer. TRDY# must connect the 
appropriate pins of all system bus agents.