Intel SR1640TH SR1640THNA ユーザーズマニュアル
製品コード
SR1640THNA
Functional Architecture
Intel® Server System SR1640TH TPS
Revision
1.0
Intel order number: E94847-001
58
2.7.2.1
CMOS Clear (J1G2, J9J1)
When enabled, all CMOS settings will be reset to default.
Table 46. CMOS Clear (J1G2, J9J1)
Name
Pin To Pin
Function
Description
Default
1-2
Normal operation
Reset 2-3 CMOS
Clear
2.7.2.2
BIOS Recovery (J1G3, J9H3)
Provide a manual mode of BIOS recovery configures.
Table 47. BIOS Recovery (J1G3, J9H3)
Name
Pin To Pin
Function
Description
Default
1-2
Normal operation
Recovery
2-3
Recovery
BIOS recovery from other media
2.7.2.3
BMC Force Update (J1A1, J5A1)
Provide a manual mode of BIOS recovery configures.
Table 48. BMC Force Update (J1A1, J5A1)
Name
Pin To Pin
Function
Description
Default
1-2
Normal operation
Enable
2-3
Enable
BMC force update
2.7.3
Board LED
Port 80 LED Displays (Diagnositc LED)
This Port 80 LEDs provide on board decoding and display of software debug information.
The Port 80 interface for the LPC bus is implemented as shown in the table below
The Port 80 interface for the LPC bus is implemented as shown in the table below
Table 49. Port 80/81 Display Interface on LPC Bus
LSB
MSB
DS6A1 DS7A3 DS7A2 DS7A1 POST
CODE
COLOR
Q4 Q5 Q6 Q7
HIGH
NIBBLE
RED
Q0 Q1 Q2 Q3
LOW
NIBBLE GREEN
0 0 0 0
0 0 0 0
0 0 0 0
0 0
OFF
0 0 0 0
1 1 1 1
1 1 1 1
0 F
GREEN
1 1 1 1
0 0 0 0
0 0 0 0
F 0
RED
1 1 1 1
F
F AMBER