Dataram DTM68300A ユーザーズマニュアル
DTM68300A
32GB - 288-Pin 4Rx4 Load Reduced ECC DDR4 LRDIMM
Document 06361, Revision A, 18-Sep-14, Dataram Corporation
© 2014
Page 1
Features
Identification
288-pin JEDEC-compliant DIMM, 133.35 mm wide by 31.25 mm
high
high
DTM68300A 4Gx72
32G 4Rx4 PC4-2133P-LD0-10
Performance range
Clock / Module Speed / CL-t
32G 4Rx4 PC4-2133P-LD0-10
Performance range
Clock / Module Speed / CL-t
RCD
-t
RP
1067 MHz / PC4-2133 / 16-16-16
1067MHz / PC4-2133 / 15-15-15
933 Hz / PC4-1866 / 14-14-14
933 Hz / PC4-1866 / 13-13-13
800 Hz / PC4-1600 / 12-12-12
800 Hz / PC4-1600 / 11-11-11
667 MHz / PC4-1600 / 9-9-9
1067MHz / PC4-2133 / 15-15-15
933 Hz / PC4-1866 / 14-14-14
933 Hz / PC4-1866 / 13-13-13
800 Hz / PC4-1600 / 12-12-12
800 Hz / PC4-1600 / 11-11-11
667 MHz / PC4-1600 / 9-9-9
Description
DTM68300A is a load reduced 4Gx72
memory module, which conforms to
JEDEC's DDR4-2133, PC4-2133 standard.
The assembly is Quad-Rank. Ranks are
comprised of Samsung 2Gbx4 DDR4-2133
DDP SDRAMs. One 4K-bit EEPROM is
used for Serial Presence Detect and a
Registering Clock Driver, with Address and
Command Parity, is also used as well as
data buffers to reduce the overall loading
on the data bus.
Both output driver strength and input
termination impedance are programmable
to maintain signal integrity on the I/O
signals in a Fly-by topology. A thermal
sensor accurately monitors the DIMM
module and can prevent exceeding the
maximum operating temperature of 95C.
memory module, which conforms to
JEDEC's DDR4-2133, PC4-2133 standard.
The assembly is Quad-Rank. Ranks are
comprised of Samsung 2Gbx4 DDR4-2133
DDP SDRAMs. One 4K-bit EEPROM is
used for Serial Presence Detect and a
Registering Clock Driver, with Address and
Command Parity, is also used as well as
data buffers to reduce the overall loading
on the data bus.
Both output driver strength and input
termination impedance are programmable
to maintain signal integrity on the I/O
signals in a Fly-by topology. A thermal
sensor accurately monitors the DIMM
module and can prevent exceeding the
maximum operating temperature of 95C.
Operating Voltage: VDD/VDDQ = 1.2V (1.14V to 1.26V)
VPP = 2.5V (2.375V to 2.75V)
VDDSPD = 2.25V to 2.75V
I/O Type: 1.2 V signaling
VDDSPD = 2.25V to 2.75V
I/O Type: 1.2 V signaling
On-board I
2
C temperature sensor with integrated Serial
Presence-Detect (SPD) EEPROM
Data Transfer Rate: 17.0 Gigabytes/sec
Data Bursts: 8 and burst chop 4 mode
ZQ Calibration for Output Driver and On-Die Termination (ODT)
Programmable ODT / Dynamic ODT during Writes
Programmable CAS Latency: 9, 11, 12, 13, 14, 15 and 16
Bi-directional Differential Data Strobe signals
Per DRAM Addressability is supported
Write CRC is supported at all speed grades
ALERT Flag Supported
CA parity (Command/Address Parity) mode is supported
Supports ECC error correction and detection
16 Internal Banks (4 Bank Groups)
SDRAM Addressing (Row/Col/BG/BA): 16/10/2/2
Write CRC is supported at all speed grades
ALERT Flag Supported
CA parity (Command/Address Parity) mode is supported
Supports ECC error correction and detection
16 Internal Banks (4 Bank Groups)
SDRAM Addressing (Row/Col/BG/BA): 16/10/2/2
Fully RoHS Compliant