Intel Quad-core Intel Xeon DP X5335 Active BX80563X5335A データシート
製品コード
BX80563X5335A
Thermal Specifications
102
Quad-Core Intel® Xeon® Processor 5300 Series Datasheet
6.3.7
THERMTRIP# Signal
Regardless of whether or not TM1 or TM2 is enabled, in the event of a catastrophic
cooling failure, the processor will automatically shut down when the silicon has reached
an elevated temperature (refer to the THERMTRIP# definition in
cooling failure, the processor will automatically shut down when the silicon has reached
an elevated temperature (refer to the THERMTRIP# definition in
). At this
point, the FSB signal THERMTRIP# will go active and stay active as described in
. THERMTRIP# activation is independent of processor activity and does not
generate any bus cycles. Intel also recommends the removal of V
TT
.
6.4
Platform Environment Control Interface (PECI)
6.4.1
Introduction
PECI offers an interface for thermal monitoring of Intel processor and chipset
components. It uses a single wire, thus alleviating routing congestion issues.
components. It uses a single wire, thus alleviating routing congestion issues.
shows an example of the PECI topology in a system with Quad-Core Intel®
Xeon® Processor 5300 Series. PECI uses CRC checking on the host side to ensure
reliable transfers between the host and client devices. Also, data transfer speeds across
the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI
interface on Quad-Core Intel® Xeon® Processor 5300 Series is disabled by default and
must be enabled through BIOS. More information on this can be found in the Conroe
and Woodcrest Processor Family BIOS Writer’s Guide.
reliable transfers between the host and client devices. Also, data transfer speeds across
the PECI interface are negotiable within a wide range (2 Kbps to 2 Mbps). The PECI
interface on Quad-Core Intel® Xeon® Processor 5300 Series is disabled by default and
must be enabled through BIOS. More information on this can be found in the Conroe
and Woodcrest Processor Family BIOS Writer’s Guide.
6.4.1.1
T
CONTROL
and TCC Activation on PECI-Based Systems
Fan speed control solutions based on PECI utilize a T
CONTROL
value stored in the
processor IA32_TEMPERATURE_TARGET MSR. This MSR uses the same offset
temperature format as PECI, though it contains no sign bit. Thermal management
devices should infer the T
temperature format as PECI, though it contains no sign bit. Thermal management
devices should infer the T
CONTROL
value as negative. Thermal management algorithms
should utilize the relative temperature value delivered over PECI in conjunction with the
MSR value to control or optimize fan speeds.
MSR value to control or optimize fan speeds.
diagram using PECI temperatures.
Figure 6-8. PECI Topology
P E C I H o s t
C o n tr o lle r
D o m a in 0
0
x
3
0
x
3
0
D o m a in 1
0
x
3
0
x
3
0
D o m a in 0
0
x
3
1
x
3
1
D o m a in 1
0
x
3
1
x
3
1
Q u a d -C o r e In te l® X e o n ®
P r o c e s s o r 5 3 0 0 S e r ie s
(S o c k e t 0 )
Q u a d -C o r e In te l® X e o n ®
P ro c e s s o r 5 3 0 0 S e rie s
(S o c k e t 1 )
G 5
G 5