Microchip Technology MCU PIC10F322T-I/OT SOT-23-6 MCP PIC10F322T-I/OT データシート
製品コード
PIC10F322T-I/OT
2011 Microchip Technology Inc.
Preliminary
DS41585A-page 101
PIC10(L)F320/322
16.0
TIMER0 MODULE
The Timer0 module is an 8-bit timer/counter with the
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
following features:
• 8-bit timer/counter register (TMR0)
• 8-bit prescaler (independent of Watchdog Timer)
• Programmable internal or external clock source
• Programmable external clock edge selection
• Interrupt on overflow
is a block diagram of the Timer0 module.
16.1
Timer0 Operation
The Timer0 module can be used as either an 8-bit timer
or an 8-bit counter.
or an 8-bit counter.
16.1.1
8-BIT TIMER MODE
The Timer0 module will increment every instruction
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the T0CS bit of the OPTION_REG
register.
cycle, if used without a prescaler. 8-Bit Timer mode is
selected by clearing the T0CS bit of the OPTION_REG
register.
When TMR0 is written, the increment is inhibited for
two instruction cycles immediately following the write.
two instruction cycles immediately following the write.
16.1.2
8-BIT COUNTER MODE
In 8-Bit Counter mode, the Timer0 module will increment
on every rising or falling edge of the T0CKI pin.
8-Bit Counter mode using the T0CKI pin is selected by
setting the T0CS bit in the OPTION_REG register to ‘1’.
The rising or falling transition of the incrementing edge
for the external input source is determined by the T0SE
bit in the OPTION_REG register.
on every rising or falling edge of the T0CKI pin.
8-Bit Counter mode using the T0CKI pin is selected by
setting the T0CS bit in the OPTION_REG register to ‘1’.
The rising or falling transition of the incrementing edge
for the external input source is determined by the T0SE
bit in the OPTION_REG register.
FIGURE 16-1:
BLOCK DIAGRAM OF THE TIMER0 PRESCALER
Note:
The value written to the TMR0 register
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
can be adjusted, in order to account for
the two instruction cycle delay when
TMR0 is written.
T0CKI
T0SE
TMR0
PS<2:0>
Data Bus
Set Flag bit TMR0IF
on Overflow
T0CS
0
1
0
1
8
8
8-bit
Prescaler
F
OSC
/4
PSA
S
YNC
2 T
CY