Microchip Technology 24LC32A-I/SN Memory IC 32 K 4 K x 8 24LC32A-I/SN データシート
製品コード
24LC32A-I/SN
2002-2012 Microchip Technology Inc.
DS21713M-page 5
24AA32A/24LC32A
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
2.1
A0, A1, A2 Chip Address Inputs
The A0, A1 and A2 inputs are used by the 24XX32A for
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V
multiple device operation. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to eight devices may be connected to the same bus
by using different Chip Select bit combinations. These
inputs must be connected to either V
CC
or V
SS
.
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 and chip scale
packages.
and A2 are hard-wired to logic ‘0’ or logic ‘1’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘0’ or logic ‘1’
before normal device operation can proceed. Address
pins are not available in the SOT-23 and chip scale
packages.
2.2
Serial Data (SDA)
SDA is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to V
and data into and out of the device. It is an open-drain
terminal, therefore, the SDA bus requires a pull-up
resistor to V
CC
(typical 10 k
for 100 kHz, 2 k for
400 kHz)
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating Start and Stop conditions.
2.3
Serial Clock (SCL)
The SCL input is used to synchronize the data transfer
to and from the device.
to and from the device.
2.4
Write-Protect (WP)
This pin must be connected to either V
SS
or V
CC
. If tied
to V
SS
, write operations are enabled. If tied to V
CC
,
write operations are inhibited but read operations are
not affected.
not affected.
Name PDIP SOIC SOIJ TSSOP
Rotated
TSSOP
DFN
(1)
TDFN
(1)
MSOP SOT-23 CS
Description
A0
1
1
1
1
3
1
1
1
—
—
Chip Address Input
A1
2
2
2
2
4
2
2
2
—
—
Chip Address Input
A2
3
3
3
3
5
3
3
3
—
—
Chip Address Input
V
SS
4
4
4
4
6
4
4
4
2
2
Ground
SDA
5
5
5
5
7
5
5
5
3
5
Serial Address/Data I/O
SCL
6
6
6
6
8
6
6
6
1
4
Serial Clock
WP
7
7
7
7
1
7
7
7
5
3
Write-Protect Input
V
CC
8
8
8
8
2
8
8
8
4
1
+1.7V to 5.5V Power Supply
Note 1: The exposed pad on the DFN/TDFN packages can be connected to V
SS
or left floating.