Microchip Technology IC MCU FLASH 4K PIC16LF88-I/P DIP-18 MCP PIC16LF88-I/P 情報ガイド
製品コード
PIC16LF88-I/P
SSP MODULE
DS80132F-page 2
© 2007 Microchip Technology Inc.
Clarifications/Corrections to the Data
Sheets
Sheets
1.
Module: SSP (SPI Mode)
The description of the operation of the CKE bit
(SSPSTAT<6>) is clarified. Please substitute the
description in Register 1, below, for all occurrences of
the existing text for the SSPSTAT register, bit 6 (new
text in bold).
(SSPSTAT<6>) is clarified. Please substitute the
description in Register 1, below, for all occurrences of
the existing text for the SSPSTAT register, bit 6 (new
text in bold).
2.
Module: SSP (SPI Slave Mode)
The description of the operation of SPI Slave mode is
clarified as follows:
clarified as follows:
Before enabling the module in SPI Slave mode, the
state of the clock line (SCK) must match the polarity
selected for the Idle state. The clock line can be
observed by reading the SCK pin. The polarity of the
Idle state is determined by the CKP bit (SSPCON<4>).
state of the clock line (SCK) must match the polarity
selected for the Idle state. The clock line can be
observed by reading the SCK pin. The polarity of the
Idle state is determined by the CKP bit (SSPCON<4>).
This foregoing text should be added to the appropriate
subsections of the “SSP Module” chapter, entitled “SPI
Mode” and read in context with any discussions of SPI
Slave mode.
subsections of the “SSP Module” chapter, entitled “SPI
Mode” and read in context with any discussions of SPI
Slave mode.
In the case of DS30234D, the text applies to both
implementations of SPI mode, as described in
Sections 11.2 and 11.3.
implementations of SPI mode, as described in
Sections 11.2 and 11.3.
REGISTER 1:
SSPSTAT: SSP STATUS REGISTER (EXCERPT)
Note:
This correction applies to the Data Sheets
for the following devices:
for the following devices:
• PIC16C62B/72A (DS35008B)
• PIC16C63A/65B/73B/74B (DS30605C)
• PIC16C923/924 (DS30444E)
• PIC16C925/926 (DS39544A)
• PIC16F72 (DS39597B)
• PIC16F73/74/76/77 (DS30325B)
• PIC18F2331/2431/4331/4431
(DS39616B)
In addition, this clarification applies only to
the following devices in the PIC16C6X
Data Sheet (DS30234D):
the following devices in the PIC16C6X
Data Sheet (DS30234D):
• PIC16C66
• PIC16C67
In addition, this clarification applies only to
the following devices in the PIC16C7X
Data Sheet (DS30390E):
the following devices in the PIC16C7X
Data Sheet (DS30390E):
• PIC16C76
• PIC16C77
Any devices not explicitly listed in this
section do not implement SPI mode and
are not affected by this clarification.
section do not implement SPI mode and
are not affected by this clarification.
Note:
This text refers only to the operation of the
CKE bit in SPI mode; its operation in I
CKE bit in SPI mode; its operation in I
2
C
mode is unchanged.
Note:
This correction applies to the Data Sheets
for the following devices:
for the following devices:
• PIC16C6X (DS30234D), except
PIC16C61 (does not implement the
SSP module)
SSP module)
• PIC16C62B/72A (DS35008B)
• PIC16C63A/65B/73B/74B (DS30605C)
• PIC16C72/73/73A/74/74A/76/77
(DS30390E)
• PIC16C923/924 (DS30444E)
• PIC16C925/926 (DS39544A)
• PIC16F72 (DS39597B)
• PIC16F73/74/76/77 (DS30325B)
• PIC18F2331/2431/4331/4431
(DS39616B)
Any other devices not explicitly listed in this
section do not implement SPI mode and
are not affected by this clarification.
section do not implement SPI mode and
are not affected by this clarification.
bit 6
CKE: SPI Clock Edge Select bit
1
= Transmit occurs on transition from active to Idle clock state
0
= Transmit occurs on transition from Idle to active clock state
Note:
Polarity of clock state is set by the CKP bit (SSPCON<4>).