Cypress Semiconductor CY3280-MBR3 データシート

Document Number: 001-85330 Rev. *G 

Page 17 of 37

, the CY8CMBR3108 device is configured in the 

following manner:

■

CS0–CS3: CapSense buttons

❐

All CapSense pins must have a 560-ohm series resistance 

(placed close to the chip) for improved noise immunity.

■

GPO0–GPO3: To external LEDs

❐

LEDs are connected in sinking mode because the 

CY8MBR3xxx devices have high sink current capability.

❐

Series resistances are connected to limit the GPO current to 

be with I

IL

 limits.

■

CMOD pin: 2.2 nF to ground

■

VCC pin: 0.1 µF to ground

■

VDD pin: To external supply voltage

❐

1-µF and 0.1-µF decoupling capacitors connected to VDD

■

VDDIO pin: To supply voltage, which is 

≤ VDD

❐

VDDIO powers I

2

C and HI lines.

❐

1-µF and 0.1-µF decoupling capacitors connected to VDDIO.

■

I2C_SCL and I2C_SDA pins: 330 ohms to the I

2

C header

❐

For I

2

C communication: It is assumed that the I

2

C line pull-up 

resistors are present on the host side outside the I

2

C header.

■

HI pin: To host 

❐

To prompt the host to initiate an I

2

C transaction for reading 

the changed sensor status.

I2C_SCL
I2C_SDA

I2C_SCL

I2C_SDA

HI

(TO HOST)

CMOD

VCC

VDD

VDD

VDD

VDD

VDD

VDDIO

VDDIO

J1

I2C HEADER

1
2
3
4
5

R4

560E

D4

C5

1uF

D2

R2

330E

R8

1K

R1

330E

CS0

R9

1K

U1

CY8CMBR3108(16-QFN)

CS0/PS0

1

CS1/PS1

2

CMOD

3

VCC

4

VDD_IO

5

VDD

6

VSS

7

CS4/GPO0

8

CS5/GPO1

9

CS6/GPO2

10

CS7/GPO3/SH

11

CS2/GUARD

12

CS3

13

I2C_SDA

14

I2C_SCL

15

HI/BUZ

16

R5

560E

D3

R3

560E

C6

0.1uF

D1

R6

1K

C4

0.1uF

C2

1uF

CS2

CS3

C1

0.1uF

C3

2.2nF

R7

1K

R10

560E

CS1

5. VCC should be connected to VDD for 1.71 V 

≤

 

VDD 

≤ 1.89 V.

6. Proper ground layout is important for better SNR performance. Refer to the 

 and 

guide for all 

layout guidelines.