Cypress Semiconductor Cy8CKIT-050 Cy8CKIT-050B ユーザーズマニュアル

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CY8CKIT-050 PSoC® 5LP Development Kit Guide, Doc. # 001-65816 Rev. *E

Code Examples

5.2.2

Hardware Connections

The example requires the character LCD on P8. Because it uses the potentiometer, the jumper
POT_PWR should be in place. This connects the potentiometer to the Vdda. Move jumper J10 and
J11 to position 2-3, this will set Vdda to 5 V.

5.2.3

Del-Sig ADC Configuration

To view or configure the Delsig ADC component, double-click the component in the TopDe-
sign.cysch

 file.

Figure 5-4.  Delta-Sigma ADC Configuration 

To configure the Del-Sig ADC:

■

Select the continuous mode of operation because the ADC scans only one channel.

■

Set the conversion rate to 187 samples/sec, which is the maximum sample rate possible at 20-bit 
resolution.

■

Set the range from Vssa to Vdda in single-ended mode because the potentiometer output is a 
single-ended signal that can go from 0 to Vdda. Therefore, at 20-bit resolution, the ADC will 

resolve in steps of Vdda/2

20

.

Note Internal Vdda/3 Reference option is not available in the current PSoC 5 silicon. In this project,
Vdda = 5 V. The project will not work if Vdda = 3.3 V, because it needs Vdda/3 reference for DelSig