Texas Instruments CDC3S04EVM - CDC3S04EVM Evaluation Module CDC3S04EVM CDC3S04EVM データシート
製品コード
CDC3S04EVM
MCLK_IN_2
CLK1
CLK2
CLK3
MCLK_IN
CLK1_1
CLK2_1
CLK4_1
CLK3_1
CLK4
MCLK_IN_1
V_LDO
1.8V_Vdd_ANA
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_ANA
Adj_V
V_LDO
1.8V_Vdd_ANA
1.8V_Vdd_ANA
1.8V_Vdd_ANA
1.8V_Vdd_ANA
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_DIG
1.8V_Vdd_ANA
REQ1
REQ2
REQ3
REQ4
MCLK_REQ
RESET
REQ1
REQ2
REQ3
REQ4
SCLH
SDAH
RESET
MCLK_REQ_P
MCLK_REQ_P
T
h
e
o
u
t
p
u
t
s
o
f
t
h
e
C
D
C
4
S
0
4
n
e
e
d
t
o
h
a
v
e
t
h
e
m
i
n
i
m
u
m
a
m
o
u
n
t
o
f
c
a
p
a
c
i
t
a
n
c
e
t
o
G
N
D
a
n
d
V
D
D
.
R29
R
DNP
R29
R
DNP
R101
10k
R101
10k
C73
100n
C73
100n
J18
SMA-EDGE
J18
SMA-EDGE
2
3
4
5
3
4
5
1
C34
100nF
C34
100nF
J73
HEADER1
J73
HEADER1
1
C8
15PF
C8
15PF
C33
10nF
C33
10nF
R99
10k
R99
10k
R98
0R
R98
0R
1
2
MH2
MHOLE1
MH2
MHOLE1
1
1
R103
10k
R103
10k
MH5
MHOLE1
MH5
MHOLE1
1
1
J21
SMA-EDGE
J21
SMA-EDGE
2
3
4
5
3
4
5
1
MH4
MHOLE1
MH4
MHOLE1
1
1
R80
500R
R80
500R
1
2
R97
0R
R97
0R
1
2
R26
R
DNP
R26
R
DNP
R30
R
DNP
R30
R
DNP
J19
SMA-EDGE
J19
SMA-EDGE
2
3
4
5
1
J20
SMA-EDGE
J20
SMA-EDGE
2
3
4
5
3
4
5
1
J17
SMA-EDGE
J17
SMA-EDGE
2
3
4
5
3
4
5
1
R124
1k
R124
1k
U4
CDC3S04
U4
CDC3S04
REQ2
A1
CLK2
A2
REQ1
A3
CLK1
A4
MCLK_IN
B1
/Reset
B2
VD
D_
AN
A
B3
GN
D_
AN
A
B4
REQ4
C1
CLK4
C2
REQ3
C3
CLK3
C4
VD
D_
DIG
D1
GN
D_
DIG
D2
MCLK_REQ
D3
ADR_A0
D4
VLDO
E1
VBA
T
E2
SDAH
E3
SCLH
E4
R95
10k
R95
10k
R31
R
DNP
R31
R
DNP
R27
R
DNP
R27
R
DNP
J66
Jumper3
J66
Jumper3
1
3
2
R125
1k
R125
1k
X1
TCXO
X1
TCXO
V
4
GND
2
GND
1
OUT
3
R94
10k
R94
10k
R32
R
DNP
R32
R
DNP
C75
100n
C75
100n
MH1
MHOLE1
MH1
MHOLE1
1
1
MH3
MHOLE1
MH3
MHOLE1
1
1
C49
100nF
C49
100nF
R102
10k
R102
10k
R28
R
DNP
R28
R
DNP
J68
Jumper3
J68
Jumper3
1
3
2
C48
800nF
C48
800nF
C55
100n
C55
100n
R123
10k
R123
10k
R1
16
10k
R1
16
10k
R106
0R0
R106
0R0
R74
500R
R74
500R
1
2
C36
100nF
C36
100nF
R104
10k
R104
10k
R33
R
DNP
R33
R
DNP
J74
Jumper3
J74
Jumper3
1
3
2
R100
10k
R100
10k
R107
22R
R107
22R
C35
10nF
C35
10nF
R96
5k1
R96
5k1
1
2
J69
Jumper3
J69
Jumper3
1
3
2
C76
100n
C76
100n
J67
Jumper3
J67
Jumper3
1
3
2
Schematic
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8
Schematic
Figure 2. Schematic – (1 of 3)
6
Quad Sine-Wave Clock Buffer Evaluation Board
SCAU040 – March 2010
Copyright © 2010, Texas Instruments Incorporated