Texas Instruments TLV320AIC3104 Evaluation Module (EVM) and USB motherboard TLV320AIC3104EVM-K TLV320AIC3104EVM-K データシート
製品コード
TLV320AIC3104EVM-K
N–1
N–1
N–1
1
1
1
1
N–1
N–2
N–2
N–2
0
0
0
0
N–2
Right-Channel Data
Right-Channel Data
Left-Channel Data
Left-Channel Data
• • • •
• • • •
• • • •
• • • • • •
DSP Mode
Left-Justified Mode
Offset
Offset
Offset
T0153-01
Word Clock
Word Clock
Bit Clock
Bit Clock
Data In/Out
Data In/Out
SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010
TDM DATA TRANSFER
Time-division multiplexed data transfer can be realized in any of the left- transfer modes if the 256-clock bit-clock
mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By changing
the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data
output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks except when
valid data is being put onto the bus. This allows other codecs to be programmed with different offsets and to
drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores
data on the bus except where it is expected, based on the programmed offset.
mode is selected, although it is recommended to be used in either left-justified mode or DSP mode. By changing
the programmable offset, the bit clock in each frame where the data begins can be changed, and the serial data
output driver (DOUT) can also be programmed to the high-impedance state during all bit clocks except when
valid data is being put onto the bus. This allows other codecs to be programmed with different offsets and to
drive their data onto the same DOUT line, just in a different slot. For incoming data, the codec simply ignores
data on the bus except where it is expected, based on the programmed offset.
Note that the location of the data when an offset is programmed is different, depending on what transfer mode is
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in
the frame. This differs from left-justified mode, where the left- and right-channel data are always a half-frame
apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left- and
right-channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in
selected. In DSP mode, both left and right channels of data are transferred immediately adjacent to each other in
the frame. This differs from left-justified mode, where the left- and right-channel data are always a half-frame
apart in each frame. In this case, as the offset is programmed from zero to some higher value, both the left- and
right-channel data move across the frame, but still stay a full half-frame apart from each other. This is depicted in
for the two cases.
Figure 22. DSP Mode and Left-Justified Mode, Showing the
Effect of a Programmed Data-Word Offset
AUDIO DATA CONVERTERS
The TLV320AIC3104 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate at
different sampling rates in various combinations, which are described further as follows.
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters also can operate at
different sampling rates in various combinations, which are described further as follows.
The data converters are based on the concept of an f
S(ref)
rate that is used internal to the part, and it is related to
the actual sampling rates of the converters through a series of ratios. For typical sampling rates, f
S(ref)
is either
44.1 kHz or 48 kHz, although it can realistically be set over a wider range of rates up to 53 kHz, with additional
restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and
also to enable high-quality playback of low-sampling-rate data, without high-frequency audible noise being
generated.
restrictions applying if the PLL is used. This concept is used to set the sampling rates of the ADC and DAC, and
also to enable high-quality playback of low-sampling-rate data, without high-frequency audible noise being
generated.
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