Texas Instruments TLV320AIC3104 Evaluation Module (EVM) and USB motherboard TLV320AIC3104EVM-K TLV320AIC3104EVM-K データシート
製品コード
TLV320AIC3104EVM-K
B0155-01
LB1
RB2
Atten
LB2
L
+
+
+
+
+
–
–
+
+
R
To Left Channel
To Right Channel
SLAS510C – FEBRUARY 2007 – REVISED DECEMBER 2010
Table 6. Default Digital Effects Processing Filter Coefficients,
When in Independent Channel Processing Configuration
Coefficients
N0 = N3
D1 = D4
N1 = N4
D2 = D5
N2 = N5
27,619
32,131
–27,034
–31,506
26,461
The digital processing also includes capability to implement 3-D processing algorithms by providing means to
process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo
output playback. The architecture of this processing mode, and the programmable filters available for use in the
system, are shown in
process the mono mix of the stereo input, and then combine this with the individual channel signals for stereo
output playback. The architecture of this processing mode, and the programmable filters available for use in the
system, are shown in
. Note that the programmable attenuation block provides a method of adjusting
the level of 3-D effect introduced into the final stereo output. This, combined with the fully programmable biquad
filters in the system, enables the user to optimize the audio effects for a particular system and provide extensive
differentiation from other systems using the same device.
filters in the system, enables the user to optimize the audio effects for a particular system and provide extensive
differentiation from other systems using the same device.
Figure 27. Architecture of the Digital Audio Processing When 3-D Effects Are Enabled
It is recommended that the digital effects filters should be disabled while the filter coefficients are being modified.
While new coefficients are being written to the device over the control port, it is possible that a filter using
partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable
audio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of
effects can be entirely avoided.
While new coefficients are being written to the device over the control port, it is possible that a filter using
partially updated coefficients may actually implement an unstable system and lead to oscillation or objectionable
audio output. By disabling the filters, changing the coefficients, and then re-enabling the filters, these types of
effects can be entirely avoided.
DIGITAL INTERPOLATION FILTER
The digital interpolation filter upsamples the output of the digital audio processing block by the required
oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21/f
oversampling ratio before data is provided to the digital delta-sigma modulator and analog reconstruction filter
stages. The filter provides a linear phase output with a group delay of 21/f
S
. In addition, programmable digital
interpolation filtering is included to provide enhanced image filtering and reduce signal images caused by the
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc.). The images at 8 kHz and 16 kHz are below 20 kHz and still
audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation
filter is designed to maintain at least 65-dB rejection of images which are below 7.455 f
upsampling process that are below 20 kHz. For example, upsampling an 8-kHz signal produces signal images at
multiples of 8-kHz (i.e., 8 kHz, 16 kHz, 24 kHz, etc.). The images at 8 kHz and 16 kHz are below 20 kHz and still
audible to the listener; therefore, they must be filtered heavily to maintain a good quality output. The interpolation
filter is designed to maintain at least 65-dB rejection of images which are below 7.455 f
S
. In order to use the
programmable interpolation capability, f
S(ref)
should be programmed to a higher rate (restricted to be in the range
of 39 kHz to 53 kHz when the PLL is in use), and the actual f
S
is set using the NCODEC divider, where
NCODEC = NDAC = NADC. For example, if f
S
= 8 kHz is required, then f
S(ref)
can be set to 48 kHz, and the DAC
f
S
set to f
S(ref)
/6. This ensures that all images of the 8-kHz data are sufficiently attenuated well beyond a 20-kHz
audible frequency range.
Copyright © 2007–2010, Texas Instruments Incorporated
33
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