Texas Instruments LM3404 Evaluation Boards LM3404FSTDIMEV/NOPB LM3404FSTDIMEV/NOPB ユーザーズマニュアル
製品コード
LM3404FSTDIMEV/NOPB
+
-
SNVS465F – OCTOBER 2006 – REVISED MAY 2013
Conduction loss, P
C
, in the internal MOSFET:
P
C
= (I
F
2
x R
DSON
) x D = (0.5
2
x 0.8) x 0.73 = 146 mW
(75)
Gate charging and VCC loss, P
G
, in the gate drive and linear regulator:
P
G
= (I
IN-OP
+ f
SW
x Q
G
) x V
IN
P
G
= (600 x 10
-6
+ 2.23 x 10
5
x 6 x 10
-9
) x 48 = 94 mW
(76)
Switching loss, P
S
, in the internal MOSFET:
P
S
= 0.5 x V
IN
x I
F
x (t
R
+ t
F
) x f
SW
P
S
= 0.5 x 48 x 0.5 x 40 x 10
-9
x 2.23 x 10
5
= 107 mW
(77)
AC rms current loss, P
CIN
, in the input capacitor:
P
CIN
= I
IN(rms)
2
x ESR = 0.222
2
0.003 = 0.1 mW (negligible)
(78)
DCR loss, P
L
, in the inductor
P
L
= I
F
2
x DCR = 0.5
2
x 0.56 = 140 mW
(79)
Recirculating diode loss, P
D
= 47 mW
Current Sense Resistor Loss, P
SNS
= 110 mW
Electrical efficiency,
η
= P
O
/ (P
O
+ Sum of all loss terms) = 17.6 / (17.6 + 0.644) = 96%
Temperature Rise in the LM3404HV IC is calculated as:
T
LM3404
= (P
C
+ P
G
+ P
S
) x
θ
JA
= (0.146 + 0.094 + 0.107) x 155 = 54°C
(80)
Layout Considerations
The performance of any switching converter depends as much upon the layout of the PCB as the component
selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and
minimum generation of unwanted EMI.
selection. The following guidelines will help the user design a circuit with maximum rejection of outside EMI and
minimum generation of unwanted EMI.
COMPACT LAYOUT
Parasitic inductance can be reduced by keeping the power path components close together and keeping the
area of the loops that high currents travel small. Short, thick traces or copper pours (shapes) are best. In
particular, the switch node (where L1, D1, and the SW pin connect) should be just large enough to connect all
three components without excessive heating from the current it carries. The LM3404/04HV operates in two
distinct cycles whose high current paths are shown in
area of the loops that high currents travel small. Short, thick traces or copper pours (shapes) are best. In
particular, the switch node (where L1, D1, and the SW pin connect) should be just large enough to connect all
three components without excessive heating from the current it carries. The LM3404/04HV operates in two
distinct cycles whose high current paths are shown in
:
Figure 32. Buck Converter Current Loops
The dark grey, inner loop represents the high current path during the MOSFET on-time. The light grey, outer loop
represents the high current path during the off-time.
represents the high current path during the off-time.
GROUND PLANE AND SHAPE ROUTING
The diagram of
is also useful for analyzing the flow of continuous current vs. the flow of pulsating
currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous
current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in
routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit
EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as
current, while those that carry current during the on-time or off-time only are pulsating currents. Preference in
routing should be given to the pulsating current paths, as these are the portions of the circuit most likely to emit
EMI. The ground plane of a PCB is a conductor and return path, and it is susceptible to noise injection just as
30
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