Texas Instruments DRV8412DDWEVM - DRV8412DDWEVM Evaluation Module DRV8412DDWEVM DRV8412DDWEVM データシート
製品コード
DRV8412DDWEVM
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Operation
Table 3. Mode Pin Configurations
MODE PINS
OUTPUT
DESCRIPTION
CONFIGURATION
M3
M2
M1
0
0
0
2 FB or 4 HB
Dual Full Bridges (two PWM inputs each full bridge) or four half bridges with cycle-by-cycle
current limit
current limit
0
0
1
2 FB or 4 HB
Dual full bridges (two PWM inputs each full bridge) or four half bridges with OC latching
shutdown (no cycle-by-cycle current limit)
shutdown (no cycle-by-cycle current limit)
0
1
0
1 PFB
Parallel full bridge with cycle-by-cycle current limit
0
1
1
1 FB
Dual Full Bridges (one PWM input each full bridge with complementary PWM on second half
bridge) with cycle-by-cycle current limit
bridge) with cycle-by-cycle current limit
1
x
x
Reserved
5
SLOU287 – January 2010
DRV8412EVM Motor Drive Evaluation Board
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