Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T データシート
製品コード
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
7.8.2
DSP Interrupts
The C64x+ DSP interrupt controller combines device events into 12 prioritized interrupts. The source for
each of the 12 CPU interrupts is user-programmable and is listed in
each of the 12 CPU interrupts is user-programmable and is listed in
. Also, the interrupt
controller controls the generation of the CPU exception, NMI, and emulation interrupts.
summarizes the C64x+ interrupt controller registers and memory locations. For more details on DSP
interrupt control, see the TMS320DM646x DMSoC DSP Subsystem Reference Guide (literature number
interrupt control, see the TMS320DM646x DMSoC DSP Subsystem Reference Guide (literature number
).
Table 7-25. DM6467T DSP Interrupts
DSP
DSP
INTERRUPT
ACRONYM
SOURCE
INTERRUPT
ACRONYM
SOURCE
NUMBER
NUMBER
0
EVT0
C64x+ Int Ctl 0
64
GPIO0
GPIO
1
EVT1
C64x+ Int Ctl 1
65
GPIO1
GPIO
2
EVT2
C64x+ Int Ctl 2
66
GPIO2
GPIO
3
EVT3
C64x+ Int Ctl 3
67
GPIO3
GPIO
4
TINTL0
Timer 0 lower – TINT12
68
GPIO4
GPIO
5
TINTH0
Timer 0 upper – TINT34
69
GPIO5
GPIO
6
TINTL1
Timer 1 lower – TINT12
70
GPIO6
GPIO
7
TINTH1
Timer 1 upper – TINT34
71
GPIO7
GPIO
8
–
Reserved
72
–
Reserved
9
EMU_DTDMA
C64x+ EMC
73
–
Reserved
10
–
Reserved
74
–
Reserved
11
EMU_RTDXRX
C64x+ RTDX
75
–
Reserved
12
EMU_RTDXTX
C64x+ RTDX
76
–
Reserved
13
IDMAINT0
C64x+ EMC 0
77
–
Reserved
14
IDMAINT1
C64x+ EMC 1
78
–
Reserved
15
–
Reserved
79
–
Reserved
16
ARM2DSP0
ARM to DSP Controller 0
80
–
Reserved
17
ARM2DSP1
ARM to DSP Controller 1
81
–
Reserved
18
ARM2DSP2
ARM to DSP Controller 2
82
–
Reserved
19
ARM2DSP3
ARM to DSP Controller 3
83
–
Reserved
20
–
Reserved
84
CCINT1
EDMA CC Region 1
21
–
Reserved
85
CCERRINT
EDMA CC Error
22
–
Reserved
86
TCERRINT0
EDMA TC0 Error
23
–
Reserved
87
TCERRINT1
EDMA TC1 Error
24
–
Reserved
88
TCERRINT2
EDMA TC2 Error
25
–
Reserved
89
TCERRINT3
EDMA TC3 Error
26
–
Reserved
90
IDEINT
ATA
27
–
Reserved
91
–
Reserved
28
–
Reserved
92
–
Reserved
29
–
Reserved
93
–
Reserved
30
–
Reserved
94
–
Reserved
31
–
Reserved
95
–
Reserved
–
Reserved
INTERR
C64x+ Interrupt Controller
32
96
Dropped CPU Interrupt Event
–
Reserved
EMC_IDMAERR
C64x+ EMC Invalid IDMA
33
97
Parameters
34
–
Reserved
98
–
Reserved
35
–
Reserved
99
–
Reserved
36
–
Reserved
100
–
Reserved
196
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