Texas Instruments AFE7070EVM Transmitter Board AFE7070EVM AFE7070EVM データシート
製品コード
AFE7070EVM
AFE7070
D[13:0]
CDCM7005
DACCLK
CLKIO
LO
RF
LVDS
SPI
USB-to-Parallel
FIFO
SPI
DAC + Modulator
Clock Synchronizer +
Jitter Cleaner
DC/DC Converter
14
4
3
DC/DC Converter
DC/DC Converter
3.3 V
1.8 V
Y1
Y3
3.3 V
10 MHz
Reference
Y4
2-Row
Header
SMA
USB
Port
SMA
SMA
SMA
Power
Jack
VCXO
REF
SMA
Hardware Overview
1
Hardware Overview
This section describes the EVM hardware and how it can be modified to evaluate the AFE7070 in various
configurations.
configurations.
1.1
EVM Block Diagram
shows a simplified block diagram of the EVM in its default configuration.
Figure 1. EVM Block Diagram
1.2
Parallel Input Data
Parallel input data is supplied to the EVM by header J8. This header can be connected to the TSW3100
CMOS outputs by a parallel CMOS connector board.
CMOS outputs by a parallel CMOS connector board.
1.3
Analog Inputs/Outputs
1.3.1
Local Oscillator
A local oscillator (LO) signal must be provided via the SMA connector J10. This signal’s amplitude must
be between –5 dBm and 5 dBm with a frequency between 100 MHz and 2.7 GHz. The signal at the SMA
connector is ac-coupled into the AFE7070’s LOP pin; LON is ac-terminated with 50
be between –5 dBm and 5 dBm with a frequency between 100 MHz and 2.7 GHz. The signal at the SMA
connector is ac-coupled into the AFE7070’s LOP pin; LON is ac-terminated with 50
Ω
.
1.3.2
External Clock Input
Provide an external clock signal by the SMA connector J4. By default, this signal is ac-coupled by a 0.01
µF capacitor and then rebiased to a common-mode dc voltage of 1.3 V at the CDCM7005’s VCXO_IN
input. The ac load impedance is 50
µF capacitor and then rebiased to a common-mode dc voltage of 1.3 V at the CDCM7005’s VCXO_IN
input. The ac load impedance is 50
Ω
. The input signal level can be between 1 V and 2.6 V peak-to-peak.
2
AFE707xEVM Evaluation Module
SLOU337 – March 2012
Copyright © 2012, Texas Instruments Incorporated