Texas Instruments SRC4382 Evaluation Module (EVM) and USB motherboard SRC4382EVM-PDK SRC4382EVM-PDK データシート

製品コード

SRC4382EVM-PDK

www.ti.com

GENERAL-PURPOSE DIGITAL OUTPUTS

HOST INTERFACE OPERATION:

SBFS030C – JANUARY 2006 – REVISED SEPTEMBER 2007

The SRC4382 includes four general-purpose digital outputs, GPO1 through GPO4 (pins 26 through 29,
respectively). A GPO pin may be programmed to a static high or low state. Alternatively, a GPO pin may be
connected to one of 14 internal logic nodes, allowing the GPO pin to inherit the function of the selected signal.
Control registers 0x1B through 0x1E are utilized to select the function of the GPO pins. For details regarding
GPO output configuration, refer to the

Control Registers

section.

Table 1

summarizes the available output

options for the GPO pins.

Table 1. General-Purpose Output Pin Configurations

GPOn3

GPOn2

GPOn1

GPOn0

GPOn FUNCTION

GPOn is forced Low (default).

GPOn is forced High.

SRC Interrupt Flag; Active Low

DIT Interrupt Flag; Active Low

DIR Interrupt Flag; Active Low

DIR 50/15

s Emphasis Flag; Active Low

DIR Non-Audio Data Flag; Active High

DIR Non-Valid Data Flag; Active High

DIR Channel Status Data Serial Output

DIR User Data Serial Output

DIR Block Start Clock Output

DIR COPY Bit Output

(0 = Copyright Asserted, 1 = Copyright Not Asserted)

DIR L (or Origination) Bit Output

(0 = 1st Generation or Higher,1 = Original)

DIR Parity Error Flag; Active High

DIR Internal Sync Clock Output; may be used as the data clock for the Channel

Status and User Data serial outputs.

DIT Internal Sync Clock

SERIAL PERIPHERAL INTERFACE (SPI) MODE

The SRC4382 supports a 4-wire SPI port when the CPM input (pin 18) is forced low or tied to ground. The SPI
port supports high-speed serial data transfers up to 40Mbps. Register and data buffer write and read operations
are supported.

The CS input (pin 19) serves as the active low chip select for the SPI port. The CS input must be forced low in
order to write or read registers and data buffers. When CS is forced high, the data at the CDIN input (pin 21) is
ignored, and the CDOUT output (pin 22) is forced to a high-impedance state. The CDIN input serves as the serial
data input for the port; the CDOUT output serves as the serial data output.

The CCLK input (pin 20) serves as the serial data clock for both the input and output data. Data is latched at the
CDIN input on the rising edge of CCLK, while data is clocked out of the CDOUT output on the falling edge of
CCLK.

Figure 75

illustrates the SPI port protocol. Byte 0 is referred to as the command byte, where the most significant

bit (or MSB) is the read/write bit. For the R/W bit, a '0' indicates a write operation, while a '1' indicates a read
operation. The remaining seven bits of the command byte are utilized for the register address targeted by the
write or read operation. Byte 1 is a don’t care byte, and may be set to all zeroes. This byte is included in order to
retain protocol compatibility with earlier Texas Instruments digital audio interface and sample rate converter
products, including the DIT4096, DIT4192, the SRC418x series devices, and the SRC419x series devices.

The SPI port supports write and read operations for multiple sequential register addresses through the
implementation of an auto-increment mode. As shown in

Figure 75

, the auto-increment mode is invoked by

simply holding the CS input low for multiple data bytes. The register address is automatically incremented after
each data byte transferred, starting with the address specified by the command byte.

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