Texas Instruments XIO2213B Evaluation Module / Reference Design XIO2213BEVM XIO2213BEVM データシート
製品コード
XIO2213BEVM
PCI Express
Transmitter
PCI Express
Receiver
PCI Bus Interface
Configuration and
Memory Register
GPIO
Serial
EEPROM
Reset
Controller
Clock
Generator
Power
Mgmt
1394b OHCI with 3-Port PHY
1394 Cable Port
1394 Cable Port
1394 Cable Port
SCPS210F – OCTOBER 2008 – REVISED MAY 2013
3
Feature/Protocol Descriptions
This chapter provides a high-level overview of all significant device features.
shows a simplified
block diagram of the basic architecture of the PCIe to PCI bridge with 1394b OHCI and 3-port PHY. The
top of the diagram is the PCIe interface, and the 1394b OHCI with 3-port PHY is located at the bottom of
the diagram.
top of the diagram is the PCIe interface, and the 1394b OHCI with 3-port PHY is located at the bottom of
the diagram.
Figure 3-1. XIO2213B Block Diagram
3.1
Power-Up/Power-Down Sequencing
The bridge contains both 1.5-V and 3.3-V power terminals. The following power-up and power-down
sequences describe how power is applied to these terminals.
sequences describe how power is applied to these terminals.
In addition, the bridge has three resets: PERST, GRST, and an internal power-on reset. These resets are
described in
described in
. The following power-up and power-down sequences describe how PERST is
applied to the bridge.
The application of the PCIe reference clock (REFCLK) is important to the power-up/-down sequence and
is included in the following power-up and power-down descriptions.
is included in the following power-up and power-down descriptions.
Copyright © 2008–2013, Texas Instruments Incorporated
Feature/Protocol Descriptions
31
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