Texas Instruments FPD Link III - DS90UB901Q & DS90UB902Q EVK SERDESUB-16USB/NOPB SERDESUB-16USB/NOPB データシート
製品コード
SERDESUB-16USB/NOPB
26
SERDESUB-16USB User’s Guide
SNLU100 – April 2012
1. Verify that LOCK LED2 is lit; This indicates the chipset is
Locked
8) After initialization, the PCLK clock and input data can begin transmission to the
Serializer. The Serializer locks onto PCLK input (if present) otherwise the on-chip
oscillator (25 MHz) is used as the input clock source. Note the user should monitor
the LOCK pin and confirm LOCK = H before performing any I2C communication
across the link.
oscillator (25 MHz) is used as the input clock source. Note the user should monitor
the LOCK pin and confirm LOCK = H before performing any I2C communication
across the link.
Figure 8. Virtual device addressing from GPU/FPGA I2C controller
I
2
C Communication over Bi-directional Control Channel in
Display Mode
This section provides instructions for a simple I2C Read/Write transaction over the bi-
directional control channel validating the interface between the host and Serializer to
Deserializer.
1) Check the Serializer DES DEV ID register 0x06 contents
2) The value entered in Serializer register 0x06 sets the target Deserializer device to
2) The value entered in Serializer register 0x06 sets the target Deserializer device to
communicate with. Load the Deserializer slave address register.
3) Host controller to load and transmit data byte to Deserializer address 0xC0
4) For verification purposes Deserializer register 0x13 General-purpose register will be
exercised for reading and writing data. Other Deserializer registers can be
programmed to check internal functions; such as register 0x03 b[0] RRFB.
programmed to check internal functions; such as register 0x03 b[0] RRFB.
5) Host controller to load and transmit write transaction to register byte 0x13 = 0xFF.
Note default of register 0x13 = 0x00.