Microchip Technology MCP9800DM-DL2 データシート

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 2004-2013 Microchip Technology Inc.
 
DS40001239E-page 15
PIC10F200/202/204/206
4.0
MEMORY ORGANIZATION
The PIC10F200/202/204/206 memories are organized
into program memory and data memory. Data memory
banks are accessed using the File Select Register
(FSR).
4.1
Program Memory Organization for 
the PIC10F200/204
The PIC10F200/204 devices have a 9-bit Program
Counter (PC) capable of addressing a 512 x 12
program memory space.
Only the first 256 x 12 (0000h-00FFh) for the
PIC10F200/204 are physically implemented (see
Figure 4-1). Accessing a location above these
boundaries will cause a wraparound within the first
256 x 12 space (PIC10F200/204). The effective
Reset vector is at 0000h (see Figure 4-1). Location
00FFh (PIC10F200/204) contains the internal clock
oscillator calibration value. This value should never
be overwritten.
FIGURE 4-1:
PROGRAM MEMORY MAP 
AND STACK FOR THE 
PIC10F200/204
CALL, RETLW
PC<7:0>
Stack Level 1
Stack Level 2
User Mem
o
ry
Sp
a
ce
9
0000h
01FFh
On-chip Program
Memory
Reset Vector
(1)
Note 1:
Address 0000h becomes the
effective Reset vector. Location 
00FFh contains the MOVLW XX 
internal oscillator calibration value.
 256 Word
00FFh
0100h