Microchip Technology MA180025 データシート
2010 Microchip Technology Inc.
DS39933D-page 157
PIC18F87J90 FAMILY
15.1.1
RTCC CONTROL REGISTERS
REGISTER 15-1:
RTCCFG: RTCC CONFIGURATION REGISTER
(1)
R/W-0
U-0
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
RTCEN
(2)
—
RTCWREN
RTCSYNC HALFSEC
(3)
RTCOE
RTCPTR1
RTCPTR0
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
RTCEN: RTCC Enable bit
(2)
1
= RTCC module is enabled
0
= RTCC module is disabled
bit 6
Unimplemented: Read as ‘0’
bit 5
RTCWREN: RTCC Value Registers Write Enable bit
1
= RTCVALH and RTCVALL registers can be written to by the user
0
= RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 4
RTCSYNC: RTCC Value Registers Read Synchronization bit
1
= RTCVALH, RTCVALL and ALRMRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
can be assumed to be valid.
0
= RTCVALH, RTCVALL and ALCFGRPT registers can be read without concern over a rollover
ripple
bit 3
HALFSEC: Half-Second Status bit
(3)
1
= Second half period of a second
0
= First half period of a second
bit 2
RTCOE: RTCC Output Enable bit
1
= RTCC clock output enabled
0
= RTCC clock output disabled
bit 1-0
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH<7:0> until it reaches ‘00’.
RTCVALH:
00
Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers.
The RTCPTR<1:0> value decrements on every read or write of RTCVALH<7:0> until it reaches ‘00’.
RTCVALH:
00
= Minutes
01
= Weekday
10
= Month
11
= Reserved
RTCVALL:
00
00
= Seconds
01
= Hours
10
= Day
11
= Year
Note 1:
The RTCCFG register is only affected by a POR. For resets other than POR, RTCC will continue to run
even if the device is in Reset.
even if the device is in Reset.
2:
A write to the RTCEN bit is only allowed when RTCWREN = 1.
3:
This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register.