Microchip Technology MA180025 データシート

 2010 Microchip Technology Inc.

DS39933D-page 177

In Compare mode, the 16-bit CCPR2 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP2
pin can be:
• driven high
• driven low
• toggled (high-to-low or low-to-high) 
• remain unchanged (that is, reflects the state of the 

I/O latch)

The action on the pin is based on the value of the mode
select bits (CCP2M<3:0>). At the same time, the
interrupt flag bit, CCP2IF, is set.

16.3.1

CCP PIN CONFIGURATION

The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.     

     

16.3.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode,
or Synchronized Counter mode, if the CCP module is
using the compare feature. In Asynchronous Counter
mode, the compare operation may not work.

16.3.3

SOFTWARE INTERRUPT MODE 

When the Generate Software Interrupt mode is chosen
(CCP2M<3:0> = 1010), the CCP2 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP2IE bit is set.

16.3.4

SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP2M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP2 can also start an
A/D conversion. In order to do this, the A/D Converter
must already be enabled.

     

Clearing the CCP2CON register will force
the RC1 or RE7 compare output latch
(depending on device configuration) to the
default low level. This is not the PORTC or
PORTE I/O data latch.

The Special Event Trigger of CCP1 only
resets Timer1/Timer3 and cannot start an
A/D conversion, even when the A/D
Converter is enabled.

Comparator

Q

S

R

Output

Logic

Special Event Trigger

Set CCP1IF

CCP1 Pin

TRIS

CCP1CON<3:0>

Output Enable

Comparator

1

0

T3CCP2

T3CCP1

Set CCP2IF

1

0

Compare

4

(Timer1 Reset)

Q

S

R

Output

Logic

Special Event Trigger

CCP2 Pin

TRIS

CCP2CON<3:0>

Output Enable

4

(Timer1/Timer3 Reset, A/D Trigger)

Match

Compare

Match