Microchip Technology MA180025 データシート
PIC18F87J90 FAMILY
DS39933D-page 250
2010 Microchip Technology Inc.
18.4.17.1
Bus Collision During a Start
Condition
Condition
During a Start condition, a bus collision occurs if:
a)
a)
SDA or SCL are sampled low at the beginning of
the Start condition (Figure 18-28).
the Start condition (Figure 18-28).
b)
SCL is sampled low before SDA is asserted low
(Figure 18-29).
(Figure 18-29).
During a Start condition, both the SDA and the SCL
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted;
• the BCLIF flag is set; and
• the MSSP module is reset to its Idle state
pins are monitored.
If the SDA pin is already low, or the SCL pin is already
low, then all of the following occur:
• the Start condition is aborted;
• the BCLIF flag is set; and
• the MSSP module is reset to its Idle state
The Start condition begins with the SDA and SCL pins
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
deasserted. When the SDA pin is sampled high, the
Baud Rate Generator is loaded from SSPADD<6:0>
and counts down to 0. If the SCL pin is sampled low
while SDA is high, a bus collision occurs, because it is
assumed that another master is attempting to drive a
data ‘1’ during the Start condition.
If the SDA pin is sampled low during this count, the
BRG is reset and the SDA line is asserted early
(Figure 18-30). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0. If the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
BRG is reset and the SDA line is asserted early
(Figure 18-30). If, however, a ‘1’ is sampled on the SDA
pin, the SDA pin is asserted low at the end of the BRG
count. The Baud Rate Generator is then reloaded and
counts down to 0. If the SCL pin is sampled as ‘0’
during this time, a bus collision does not occur. At the
end of the BRG count, the SCL pin is asserted low.
FIGURE 18-28:
BUS COLLISION DURING START CONDITION (SDA ONLY)
Note:
The reason that bus collision is not a factor
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
during a Start condition is that no two bus
masters can assert a Start condition at the
exact same time. Therefore, one master
will always assert SDA before the other.
This condition does not cause a bus
collision because the two masters must be
allowed to arbitrate the first address
following the Start condition. If the address
is the same, arbitration must be allowed to
continue into the data portion, Repeated
Start or Stop conditions.
SDA
SCL
SEN
SDA sampled low before
SDA goes low before the SEN bit is set.
S bit and SSPIF set because
MSSP module reset into Idle state.
SEN cleared automatically because of bus collision.
S bit and SSPIF set because
Set SEN, enable Start
condition if SDA = 1, SCL = 1
condition if SDA = 1, SCL = 1
SDA = 0, SCL = 1.
BCLIF
SSPIF
SDA = 0, SCL = 1.
SSPIF and BCLIF are
cleared in software
SSPIF and BCLIF are
cleared in software
Set BCLIF,
Start condition. Set BCLIF.
S