Microchip Technology MA180025 データシート

 2010 Microchip Technology Inc.

DS39933D-page 267

PIC18F87J90 FAMILY

FIGURE 19-7:

ASYNCHRONOUS RECEPTION

TABLE 19-6:

REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on Page

INTCON

GIE/GIEH PEIE/GIEL TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

—

ADIF

RC1IF

TX1IF

SSPIF

—

TMR2IF

TMR1IF

PIE1

—

ADIE

RC1IE

TX1IE

SSPIE

—

TMR2IE

TMR1IE

IPR1

—

ADIP

RC1IP

TX1IP

SSPIP

—

TMR2IP

TMR1IP

RCSTA1

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

RCREG1

EUSART Receive Register

TXSTA1

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

BAUDCON1

ABDOVF

RCIDL

RXDTP

TXCKP

BRG16

—

WUE

ABDEN

SPBRGH1

EUSART Baud Rate Generator Register High Byte

SPBRG1

EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.

Start

bit

bit 7/8

bit 1

bit 0

bit 7/8

bit 0

Stop

bit

Start

bit

Start

bit

bit 7/8

Stop

bit

RX1 (pin)

Rcv Buffer Reg

Rcv Shift Reg

Read Rcv

Buffer Reg

RCREG1

RC1IF
(Interrupt Flag)

OERR bit

CREN bit

Word 1

RCREG1

Word 2

RCREG1

Stop

bit

Note: This timing diagram shows three words appearing on the RX1 input. The RCREG1 (Receive Buffer register) is read after the third word

causing the OERR (Overrun) bit to be set.