Microchip Technology MA180025 データシート
2010 Microchip Technology Inc.
DS39933D-page 273
PIC18F87J90 FAMILY
19.5
EUSART Synchronous Slave Mode
Synchronous Slave mode is entered by clearing bit,
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK1 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
Low-Power mode.
CSRC (TXSTA<7>). This mode differs from the
Synchronous Master mode in that the shift clock is
supplied externally at the CK1 pin (instead of being
supplied internally in Master mode). This allows the
device to transfer or receive data while in any
Low-Power mode.
19.5.1
EUSART SYNCHRONOUS SLAVE
TRANSMIT
TRANSMIT
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep mode.
If two words are written to the TXREG1 and then the
SLEEP
modes is identical except in the case of Sleep mode.
If two words are written to the TXREG1 and then the
SLEEP
instruction is executed, the following will occur:
a)
The first word will immediately transfer to the
TSR register and transmit.
TSR register and transmit.
b)
The second word will remain in the TXREG1
register.
register.
c)
Flag bit, TX1IF, will not be set.
d)
When the first word has been shifted out of TSR,
the TXREG1 register will transfer the second
word to the TSR and flag bit, TX1IF, will now be
set.
the TXREG1 register will transfer the second
word to the TSR and flag bit, TX1IF, will now be
set.
e)
If enable bit, TX1IE, is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
To set up a Synchronous Slave Transmission:
1.
1.
Enable the synchronous slave serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2.
Clear bits, CREN and SREN.
3.
If interrupts are desired, set enable bit, TX1IE.
4.
If 9-bit transmission is desired, set bit, TX9.
5.
Enable the transmission by setting enable bit,
TXEN.
TXEN.
6.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit, TX9D.
should be loaded in bit, TX9D.
7.
Start transmission by loading data to the
TXREG1 register.
TXREG1 register.
8.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 19-9:
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
—
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
PIE1
—
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
IPR1
—
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
TXREG1
EUSART Transmit Register
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
BAUDCON1 ABDOVF
RCIDL
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
SPBRGH1
EUSART Baud Rate Generator Register High Byte
SPBRG1
EUSART Baud Rate Generator Register Low Byte
LATG
U2OD
U1OD
—
LATG4
LATG3
LATG2
LATG1
LATG0
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.