Microchip Technology MA180025 データシート
2010 Microchip Technology Inc.
DS39933D-page 413
PIC18F87J90 FAMILY
FIGURE 28-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND
POWER-UP TIMER TIMING
POWER-UP TIMER TIMING
TABLE 28-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol
Characteristic
Min
Typ
Max
Units
Conditions
30
T
MC
L
MCLR Pulse Width (low)
2 T
CY
10
T
CY
—
(Note 1)
31
T
WDT
Watchdog Timer Time-out Period
(no postscaler)
(no postscaler)
3.4
4.0
4.6
ms
32
T
OST
Oscillation Start-up Timer Period
1024 T
OSC
—
1024 T
OSC
T
OSC
= OSC1 period
33
T
PWRT
Power-up Timer Period
45.8
65.5
85.2
ms
34
T
IOZ
I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
Low or Watchdog Timer Reset
—
2
—
µs
38
T
CSD
CPU Start-up Time
—
10
—
µs
200
µs
Voltage Regulator
enabled and put to
sleep
enabled and put to
sleep
39
T
IOBST
Time for INTOSC to Stabilize
—
1
—
µs
Note 1: To ensure device Reset, MCLR must be low for at least 2 T
CY
or 400
s, whichever is lower.
V
DD
MCLR
Internal
POR
PWRT
Time-out
Oscillator
Time-out
Internal
Reset
Watchdog
Timer
Reset
33
32
30
31
34
I/O pins
34
Note:
Refer to Figure 28-3 for load conditions.