Microchip Technology MCP1256/7/8/9EV データシート
2006-2013 Microchip Technology Inc.
DS21989B-page 11
MCP1256/7/8/9
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
3.1
Status Indication (PGOOD, LBO)
3.1.1
POWER-GOOD OUTPUT PIN
(PGOOD)
(PGOOD)
MCP1256/8: PGOOD is high impedance when the out-
put voltage is in regulation. A logic low is asserted
when the output falls 7% (typical) below the nominal
value. The PGOOD output remains low until V
put voltage is in regulation. A logic low is asserted
when the output falls 7% (typical) below the nominal
value. The PGOOD output remains low until V
OUT
is
within 3% (typical) of its nominal value. On start-up, this
pin indicates when the output voltage reaches its final
value. PGOOD is high impedance when SHDN is low
or when BYPASS is low (MCP1258).
pin indicates when the output voltage reaches its final
value. PGOOD is high impedance when SHDN is low
or when BYPASS is low (MCP1258).
3.1.2
LOW-BATTERY OUTPUT PIN (LBO)
MCP1257/9: LBO is high impedance when the input
voltage is above the low-battery threshold voltage. A
logic low is asserted when the input falls below the low-
battery threshold voltage. The LBO output remains low
until V
voltage is above the low-battery threshold voltage. A
logic low is asserted when the input falls below the low-
battery threshold voltage. The LBO output remains low
until V
IN
is above the low-battery threshold voltage plus
the low-battery hysteresis voltage. LBO is high
impedance when SHDN is low or when BYPASS is low
(MCP1259).
impedance when SHDN is low or when BYPASS is low
(MCP1259).
3.2
Mode Selection (SLEEP, BYPASS)
3.2.1
ACTIVE LOW SLEEP MODE
(SLEEP)
(SLEEP)
MCP1256/7: A logic low signal applied to this pin
places the device into a SLEEP mode of operation. In
this mode, the device maintains regulation. SLEEP
mode performs pulse skip operation reducing the
current draw of the device at the expense of increased
output voltage ripple.
places the device into a SLEEP mode of operation. In
this mode, the device maintains regulation. SLEEP
mode performs pulse skip operation reducing the
current draw of the device at the expense of increased
output voltage ripple.
3.2.2
ACTIVE LOW BYPASS MODE
(BYPASS)
(BYPASS)
MCP1258/9: A logic low signal applied to this pin
places the device into a BYPASS mode of operation. In
this mode, the input supply voltage is connected
directly to the output.
places the device into a BYPASS mode of operation. In
this mode, the input supply voltage is connected
directly to the output.
3.3
Flying Capacitor Negative (C2-)
A 1 µF ceramic flying capacitor is recommended.
3.4
Flying Capacitor Positive (C1+)
A 1 µF ceramic flying capacitor is recommended.
3.5
Regulated Output Voltage (V
OUT
)
Regulated 3.3V output. Bypass to GND with a
minimum of 2.2 µF.
minimum of 2.2 µF.
3.6
Flying Capacitor Positive (C2+)
A 1 µF ceramic flying capacitor is recommended.
3.7
Power Supply Input Voltage (V
IN
)
A supply voltage of 1.8V to 3.6V is recommended.
Bypass to GND with a minimum of 1 µF.
Bypass to GND with a minimum of 1 µF.
3.8
Flying Capacitor Negative (C1-)
A 1 µF ceramic flying capacitor is recommended.
3.9
0V Reference (GND)
Connect to negative terminal of and input supply.
3.10
Device Shut Down (SHDN)
A logic low signal applied to this pin disables the
device. A logic high signal applied to this pin allows
normal operation.
device. A logic high signal applied to this pin allows
normal operation.
Pin No.
Symbol
Function
DFN
MSOP
1
1
PGOOD
Power-Good Indication Open-Drain Output Pin: MCP1256 and MCP1258
LBO
Low-Battery Indication Open-Drain Output Pin: MCP1257 and MCP1259
2
2
SLEEP
Active Low SLEEP Mode Input Pin: MCP1256 and MCP1257
BYPASS
Active Low BYPASS Mode Input Pin: MCP1258 and MCP1259
3
3
C2-
Flying Capacitor Negative Pin
4
4
C1+
Flying Capacitor Positive Pin
5
5
V
OUT
Regulated 3.3V Output Voltage
6
6
C2+
Flying Capacitor Positive Pin
7
7
V
IN
Power Supply Input Voltage
8
8
C1-
Flying Capacitor Negative Pin
9
9
GND
0V Reference
10
10
SHDN
Active Low SHUTDOWN Mode Input Pin