Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 108
Preliminary
2010 Microchip Technology Inc.
10.3
PORTB, TRISB and
LATB Registers
LATB Registers
PORTB is an 8-bit wide, bidirectional port. The
corresponding Data Direction and Output Latch registers
are TRISB and LATB. All pins on PORTB are digital only
and tolerate voltages up to 5.5V.
corresponding Data Direction and Output Latch registers
are TRISB and LATB. All pins on PORTB are digital only
and tolerate voltages up to 5.5V.
EXAMPLE 10-2:
INITIALIZING PORTB
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
single control bit can turn on all the pull-ups. This is
performed by clearing bit, RBPU (INTCON2<7>). The
weak pull-up is automatically turned off when the port
pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
Four of the PORTB pins (RB<7:4>) have an
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB<7:4> pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB<7:4>) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB<7:4> are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a) Any read or write of PORTB (except with the
interrupt-on-change feature. Only pins configured as
inputs can cause this interrupt to occur (i.e., any
RB<7:4> pin configured as an output is excluded from
the interrupt-on-change comparison). The input pins (of
RB<7:4>) are compared with the old value latched on
the last read of PORTB. The “mismatch” outputs of
RB<7:4> are ORed together to generate the RB Port
Change Interrupt with Flag bit, RBIF (INTCON<0>).
This interrupt can wake the device from
power-managed modes. The user, in the Interrupt
Service Routine, can clear the interrupt in the following
manner:
a) Any read or write of PORTB (except with the
MOVFF (ANY), PORTB instruction). This will end
the mismatch condition.
the mismatch condition.
b) Wait one instruction cycle.
c)
c)
Clear flag bit, RBIF.
A mismatch condition will continue to set flag bit, RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after a delay of one
T
Reading PORTB will end the mismatch condition and
allow flag bit, RBIF, to be cleared after a delay of one
T
CY
.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB<3:2> are multiplexed as CTMU edge inputs.
RB<5:0> are also multiplexed with LCD segment
drives, controlled by bits in the LCDSE1 and LCDSE3
registers. I/O port functionality is only available when
the LCD segments are disabled.
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB<3:2> are multiplexed as CTMU edge inputs.
RB<5:0> are also multiplexed with LCD segment
drives, controlled by bits in the LCDSE1 and LCDSE3
registers. I/O port functionality is only available when
the LCD segments are disabled.
CLRF
PORTB
; Initialize PORTB by
; clearing output
; data latches
; clearing output
; data latches
CLRF
LATB
; Alternate method
; to clear output
; data latches
; to clear output
; data latches
MOVLW
0CFh
; Value used to
; initialize data
; direction
; initialize data
; direction
MOVWF
TRISB
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs