Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 210
Preliminary
2010 Microchip Technology Inc.
18.4.3.2
Address Masking
Masking an address bit causes that bit to become a
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 18-2).
The I
“don’t care”. When one address bit is masked, two
addresses will be Acknowledged and cause an
interrupt. It is possible to mask more than one address
bit at a time, which makes it possible to Acknowledge
up to 31 addresses in 7-bit mode and up to
63 addresses in 10-bit mode (see Example 18-2).
The I
2
C Slave behaves the same way whether address
masking is used or not. However, when address
masking is used, the I
masking is used, the I
2
C slave can Acknowledge
multiple addresses and cause interrupts. When this
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
In 7-Bit Addressing mode, Address Mask bits,
ADMSK<5:1> (SSPCON<5:1>), mask the correspond-
ing address bits in the SSPADD register. For any ADMSK
bits that are set (ADMSK<x> = 1), the corresponding
address bit is ignored (SSPADD<x> = x). For the module
to issue an address Acknowledge, it is sufficient to match
only on addresses that do not have an active address
mask.
occurs, it is necessary to determine which address
caused the interrupt by checking SSPBUF.
In 7-Bit Addressing mode, Address Mask bits,
ADMSK<5:1> (SSPCON<5:1>), mask the correspond-
ing address bits in the SSPADD register. For any ADMSK
bits that are set (ADMSK<x> = 1), the corresponding
address bit is ignored (SSPADD<x> = x). For the module
to issue an address Acknowledge, it is sufficient to match
only on addresses that do not have an active address
mask.
In 10-Bit Addressing mode, ADMSK<5:2> bits mask
the corresponding address bits in the SSPADD regis-
ter. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPADD<1:0>). For any ADMSK
bits that are active (ADMSK<x> = 1), the correspond-
ing address bit is ignored (SSPADD<x> = x). Also note,
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits; the
address mask bits do not interact with those bits. They
only affect the lower address bits.
the corresponding address bits in the SSPADD regis-
ter. In addition, ADMSK1 simultaneously masks the two
LSbs of the address (SSPADD<1:0>). For any ADMSK
bits that are active (ADMSK<x> = 1), the correspond-
ing address bit is ignored (SSPADD<x> = x). Also note,
that although in 10-Bit Addressing mode, the upper
address bits reuse part of the SSPADD register bits; the
address mask bits do not interact with those bits. They
only affect the lower address bits.
EXAMPLE 18-2:
ADDRESS MASKING EXAMPLES
Note 1: ADMSK1 masks the two Least Significant
bits of the address.
2: The two Most Significant bits of the
address are not affected by address
masking.
masking.
7-Bit Addressing:
SSPADD<7:1> = A0h (1010000) (SSPADD<0> is assumed to be ‘0’)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A2h, A4h, A6h, A8h, AAh, ACh, AEh
10-Bit Addressing:
SSPADD<7:0> = A0h (10100000) (the two MSbs of the address are ignored in this example, since they are
not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh
not affected by masking)
ADMSK<5:1> = 00111
Addresses Acknowledged: A0h, A1h, A2h, A3h, A4h, A5h, A6h, A7h, A8h, A9h, AAh, ABh, ACh, ADh, AEh, AFh