Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 227
PIC18F87J72 FAMILY
18.4.8
I
2
C MASTER MODE START
CONDITION TIMING
To initiate a Start condition, the user sets the Start
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (T
Enable bit, SEN (SSPCON2<0>). If the SDA and SCL
pins are sampled high, the Baud Rate Generator is
reloaded with the contents of SSPADD<6:0> and starts
its count. If SCL and SDA are both sampled high when
the Baud Rate Generator times out (T
BRG
), the SDA
pin is driven low. The action of the SDA being driven
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (T
low while SCL is high is the Start condition and causes
the S bit (SSPSTAT<3>) to be set. Following this, the
Baud Rate Generator is reloaded with the contents of
SSPADD<6:0> and resumes its count. When the Baud
Rate Generator times out (T
BRG
), the SEN bit
(SSPCON2<0>) will automatically be cleared by
hardware. The Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
hardware. The Baud Rate Generator is suspended,
leaving the SDA line held low and the Start condition is
complete.
18.4.8.1
WCOL Status Flag
If the user writes the SSPBUF when a Start sequence
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
is in progress, the WCOL is set and the contents of the
buffer are unchanged (the write doesn’t occur).
FIGURE 18-21:
FIRST START BIT TIMING
Note:
If, at the beginning of the Start condition,
the SDA and SCL pins are already
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs. The Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I
the SDA and SCL pins are already
sampled low, or if during the Start condi-
tion, the SCL line is sampled low before
the SDA line is driven low, a bus collision
occurs. The Bus Collision Interrupt Flag,
BCLIF, is set, the Start condition is aborted
and the I
2
C module is reset into its Idle
state.
Note:
Because queueing of events is not
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
allowed, writing to the lower 5 bits of
SSPCON2 is disabled until the Start
condition is complete.
SDA
SCL
S
T
BRG
1st bit
2nd bit
T
BRG
SDA = 1,
At completion of Start bit,
SCL = 1
Write to SSPBUF occurs here
T
BRG
hardware clears SEN bit
T
BRG
Write to SEN bit occurs here
Set S bit (SSPSTAT<3>)
and sets SSPIF bit