Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 249
PIC18F87J72 FAMILY
FIGURE 19-4:
ASYNCHRONOUS TRANSMISSION
FIGURE 19-5:
ASYNCHRONOUS TRANSMISSION (BACK TO BACK)
TABLE 19-5:
REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR1
—
ADIF
RC1IF
TX1IF
SSPIF
—
TMR2IF
TMR1IF
PIE1
—
ADIE
RC1IE
TX1IE
SSPIE
—
TMR2IE
TMR1IE
IPR1
—
ADIP
RC1IP
TX1IP
SSPIP
—
TMR2IP
TMR1IP
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
TXREG1
EUSART Transmit Register
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
BAUDCON1 ABDOVF
RCMT
RXDTP
TXCKP
BRG16
—
WUE
ABDEN
SPBRGH1
EUSART Baud Rate Generator Register High Byte
SPBRG1
EUSART Baud Rate Generator Register Low Byte
LATG
U2OD
U1OD
—
LATG4
LATG3
LATG2
LATG1
LATG0
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Word 1
Word 1
Transmit Shift Reg
Start bit
bit 0
bit 1
bit 7/8
Write to TXREG1
BRG Output
(Shift Clock)
TX1 (pin)
TX1IF bit
(Transmit Buffer
Reg. Empty Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
1 T
CY
Word 1
Stop bit
Transmit Shift Reg.
Write to TXREG1
BRG Output
(Shift Clock)
TX1 (pin)
TX1IF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0
bit 1
bit 7/8
bit 0
Note: This timing diagram shows two consecutive transmissions.
1 T
CY
1 T
CY
Start bit