Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 270
Preliminary
2010 Microchip Technology Inc.
20.4.2
AUSART SYNCHRONOUS
MASTER RECEPTION
MASTER RECEPTION
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA2<5>), or the Continuous Receive
Enable bit, CREN (RCSTA2<4>). Data is sampled on
the RX2 pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA2<5>), or the Continuous Receive
Enable bit, CREN (RCSTA2<4>). Data is sampled on
the RX2 pin on the falling edge of the clock.
If enable bit, SREN, is set, only a single word is
received. If enable bit, CREN, is set, the reception is
continuous until CREN is cleared. If both bits are set,
then CREN takes precedence.
To set up a Synchronous Master Reception:
1.
Initialize the SPBRG2 register for the appropriate
baud rate.
baud rate.
2.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
setting bits, SYNC, SPEN and CSRC.
3.
Ensure bits, CREN and SREN, are clear.
4.
If interrupts are desired, set enable bit, RC2IE.
5.
If 9-bit reception is desired, set bit, RX9.
6.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
For continuous reception, set bit, CREN.
7.
Interrupt flag bit, RC2IF, will be set when recep-
tion is complete and an interrupt will be generated
if the enable bit, RC2IE, was set.
tion is complete and an interrupt will be generated
if the enable bit, RC2IE, was set.
8.
Read the RCSTA2 register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
enabled) and determine if any error occurred
during reception.
9.
Read the 8-bit received data by reading the
RCREG2 register.
RCREG2 register.
10. If any error occurred, clear the error by clearing
bit, CREN.
11. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
set.
FIGURE 20-8:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 20-7:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
PIR3
—
LCDIF
RC2IF
TX2IF
CTMUIF
CCP2IF
CCP1IF
RTCCIF
52
PIE3
—
LCDIE
RC2IE
TX2IE
CTMUIE
CCP2IE
CCP1IE
RTCCIE
IPR3
—
LCDIP
RC2IP
TX2IP
CTMUIP
CCP2IP
CCP1IP
RTCCIP
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCREG2 AUSART Receive Register
TXSTA2
CSRC
TX9
TXEN
SYNC
—
BRGH
TRMT
TX9D
SPBRG2
AUSART Baud Rate Generator Register
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
CREN bit
RX2/DT2 pin
TX2/CK2 pin
Write to
bit SREN
SREN bit
RC2IF bit
(Interrupt)
Read
RCREG2
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q2
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Q1 Q2 Q3 Q4
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.