Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 284
Preliminary
2010 Microchip Technology Inc.
22.1
Functional Overview
While it is convenient to think of the dual-channel AFE
as a high-precision ADC, there are actually many more
components involved. The main components are
described below. The dual-channel AFE reference
provides more in-depth information on each.
as a high-precision ADC, there are actually many more
components involved. The main components are
described below. The dual-channel AFE reference
provides more in-depth information on each.
22.1.1
DELTA-SIGMA ADC
ARCHITECTURE
ARCHITECTURE
Each Delta-Sigma ADC is an oversampling converter
that incorporates a built-in modulator which is digitizing
the quantity of charge integrated by the modulator loop.
The quantizer is the block that is performing the
analog-to-digital conversion. The quantizer is typically
1-bit, or a simple comparator, which helps to maintain
the linearity performance of the ADC (the DAC
structure is, in this case, inherently linear).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADCs.
The 5-level quantizer is a Flash ADC composed of
4 comparators arranged with equally spaced thresholds
and a thermometer coding. The AFE also includes pro-
prietary 5-level DAC architecture that is inherently linear
for improved THD figures.
The resulting channel data is either a 16-bit or 24-bit
word, presented in 23-bit or 15-bit plus sign, two’s
complement format and is MSb (left) justified.
that incorporates a built-in modulator which is digitizing
the quantity of charge integrated by the modulator loop.
The quantizer is the block that is performing the
analog-to-digital conversion. The quantizer is typically
1-bit, or a simple comparator, which helps to maintain
the linearity performance of the ADC (the DAC
structure is, in this case, inherently linear).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADCs.
The 5-level quantizer is a Flash ADC composed of
4 comparators arranged with equally spaced thresholds
and a thermometer coding. The AFE also includes pro-
prietary 5-level DAC architecture that is inherently linear
for improved THD figures.
The resulting channel data is either a 16-bit or 24-bit
word, presented in 23-bit or 15-bit plus sign, two’s
complement format and is MSb (left) justified.
22.1.2
ANALOG INPUTS (CHn+/-)
The analog inputs can be connected directly to current
and voltage transducers. Each input pin is protected by
specialized ESD structures that are certified to pass
7 kV HBM and 400V MM contact charge. These
structures allow bipolar ±6V continuous voltage with
respect to SAV
and voltage transducers. Each input pin is protected by
specialized ESD structures that are certified to pass
7 kV HBM and 400V MM contact charge. These
structures allow bipolar ±6V continuous voltage with
respect to SAV
SS
, to be present at their inputs without
the risk of permanent damage.
22.1.3
PROGRAMMABLE GAIN
AMPLIFIERS (PGA)
AMPLIFIERS (PGA)
The two Programmable Gain Amplifiers (PGAs) reside
at the front-end of each Delta-Sigma ADC. They have
two functions: translate the common-mode of the input
from SAVss to an internal level between SAV
at the front-end of each Delta-Sigma ADC. They have
two functions: translate the common-mode of the input
from SAVss to an internal level between SAV
SS
and
SAV
DD
, and amplify the input differential signal. The
translation of the common-mode does not change the
differential signal, but recenters the common-mode so
that the input signal can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
modulator must not be exceeded.
differential signal, but recenters the common-mode so
that the input signal can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
modulator must not be exceeded.
22.1.4
SINC
3
FILTER
Both ADCs include a decimation filter that is a
third-order sinc (or notch) filter. This filter processes the
multi-bit stream into either 16-bit or 24-bit words,
depending on the configuration chosen. The settling
time of the filter is three DMCLK periods. The resolution
achievable at the output of the sinc filter (the output of
the ADC) is dependent on the oversampling ratio
selected.
third-order sinc (or notch) filter. This filter processes the
multi-bit stream into either 16-bit or 24-bit words,
depending on the configuration chosen. The settling
time of the filter is three DMCLK periods. The resolution
achievable at the output of the sinc filter (the output of
the ADC) is dependent on the oversampling ratio
selected.
22.1.4.1
Internal Voltage Reference
The AFE contains an internal voltage reference source
specially designed to minimize drift over temperature.
This internal V
specially designed to minimize drift over temperature.
This internal V
REF
supplies reference voltage to both
channels. The typical value of this voltage reference is
2.37V ±2%. The internal reference has a very low typi-
cal temperature coefficient of ±12 ppm/°C, allowing the
output codes to have minimal variation with respect to
temperature since they are proportional to (1/V
2.37V ±2%. The internal reference has a very low typi-
cal temperature coefficient of ±12 ppm/°C, allowing the
output codes to have minimal variation with respect to
temperature since they are proportional to (1/V
REF
).
The output pin for the internal voltage reference is
REFIN+/OUT.
Optionally, the AFE can be configured to use an exter-
nal voltage reference supplied on the REFIN+ and
REFIN- pins.
REFIN+/OUT.
Optionally, the AFE can be configured to use an exter-
nal voltage reference supplied on the REFIN+ and
REFIN- pins.
22.1.5
PHASE DELAY BLOCK
The AFE incorporates a phase delay generator which
ensures that the two ADCs are converting the inputs
with a fixed delay between them. The two ADCs are
synchronously sampling but the averaging of
modulator outputs is delayed, so that the SINC filter
outputs (thus, the ADC outputs) show a fixed phase
delay, configured by the PHASE register.
ensures that the two ADCs are converting the inputs
with a fixed delay between them. The two ADCs are
synchronously sampling but the averaging of
modulator outputs is delayed, so that the SINC filter
outputs (thus, the ADC outputs) show a fixed phase
delay, configured by the PHASE register.
22.1.6
INTERNAL AFE CLOCK
The AFE uses an external clock signal to operate its
internal digital logic. The AFE includes a clock genera-
tion chain of back-to-back dividers to produce a range
of sampling frequencies.
internal digital logic. The AFE includes a clock genera-
tion chain of back-to-back dividers to produce a range
of sampling frequencies.
22.1.7
SERIAL INTERFACE
The AFE uses an SPI-compatible slave serial interface.
Its operation is discussed in Section 22.3 “Serial
Interface”.
Its operation is discussed in Section 22.3 “Serial
Interface”.