Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 316
Preliminary
2010 Microchip Technology Inc.
REGISTER 25-2:
CTMUCONL: CTMU CONTROL LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EDG2POL
EDG2SEL1
EDG2SEL0
EDG1POL
EDG1SEL1
EDG1SEL0
EDG2STAT
EDG1STAT
bit 7
bit 0
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EDG2POL: Edge 2 Polarity Select bit
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
1 = Edge 2 is programmed for a positive edge response
0 = Edge 2 is programmed for a negative edge response
bit 6-5
EDG2SEL<1:0>: Edge 2 Source Select bits
11 = CTEDG1 pin
10 = CTEDG2 pin
01 = CCP1 Special Event Trigger
00 = CCP2 Special Event Trigger
11 = CTEDG1 pin
10 = CTEDG2 pin
01 = CCP1 Special Event Trigger
00 = CCP2 Special Event Trigger
bit 4
EDG1POL: Edge 1 Polarity Select bit
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
1 = Edge 1 is programmed for a positive edge response
0 = Edge 1 is programmed for a negative edge response
bit 3-2
EDG1SEL<1:0>: Edge 1 Source Select bits
11 = CTEDG1 pin
10 = CTEDG2 pin
01 = CCP1 Special Event Trigger
00 = CCP2 Special Event Trigger
11 = CTEDG1 pin
10 = CTEDG2 pin
01 = CCP1 Special Event Trigger
00 = CCP2 Special Event Trigger
bit 1
EDG2STAT: Edge 2 Status bit
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
1 = Edge 2 event has occurred
0 = Edge 2 event has not occurred
bit 0
EDG1STAT: Edge 1 Status bit
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred
1 = Edge 1 event has occurred
0 = Edge 1 event has not occurred