Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 328
Preliminary
2010 Microchip Technology Inc.
26.3.2
ON-CHIP REGULATOR AND BOR
When the on-chip regulator is enabled, PIC18F87J72
family devices also have a simple Brown-out Reset
capability. If the voltage supplied to the regulator falls to
a level that is inadequate to maintain a regulated output
for full-speed operation, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON<0>).
The operation of the BOR is described in more detail in
Section 5.4 “Brown-out Reset (BOR)” and
Section 5.4.1 “Detecting BOR”.
family devices also have a simple Brown-out Reset
capability. If the voltage supplied to the regulator falls to
a level that is inadequate to maintain a regulated output
for full-speed operation, the regulator Reset circuitry
will generate a Brown-out Reset. This event is captured
by the BOR flag bit (RCON<0>).
The operation of the BOR is described in more detail in
Section 5.4 “Brown-out Reset (BOR)” and
Section 5.4.1 “Detecting BOR”.
26.3.3
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
requirements for the device. If the application does not
use the regulator, then strict power-up conditions must
be adhered to. While powering up, V
DDCORE
must
never exceed V
DD
by 0.3 volts.
26.3.4
OPERATION IN SLEEP MODE
When enabled, the on-chip regulator always consumes
a small incremental amount of current over I
a small incremental amount of current over I
DD
. This
includes when the device is in Sleep mode, even
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON<7>). Setting this bit disables
the regulator in Sleep mode and reduces its current
consumption to a minimum.
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to ensure the
regulator has enough time to stabilize.
though the core digital logic does not require power. To
provide additional savings in applications where power
resources are critical, the regulator can be configured
to automatically disable itself whenever the device
goes into Sleep mode. This feature is controlled by the
REGSLP bit (WDTCON<7>). Setting this bit disables
the regulator in Sleep mode and reduces its current
consumption to a minimum.
Substantial Sleep mode power savings can be
obtained by setting the REGSLP bit, but device
wake-up time will increase in order to ensure the
regulator has enough time to stabilize.
The REGSLP bit is automatically cleared by hardware
when a Low-Voltage Detect condition occurs. The
REGSLP bit can be set again in software, which would
continue to keep the voltage regulator in Low-Power
mode. This, however, is not recommended if any write
operations to the Flash will be performed.
when a Low-Voltage Detect condition occurs. The
REGSLP bit can be set again in software, which would
continue to keep the voltage regulator in Low-Power
mode. This, however, is not recommended if any write
operations to the Flash will be performed.
26.4
Two-Speed Start-up
The Two-Speed Start-up feature helps to minimize the
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an OST start-up delay,
Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
latency period, from oscillator start-up to code execu-
tion, by allowing the microcontroller to use the INTRC
oscillator as a clock source until the primary clock
source is available. It is enabled by setting the IESO
Configuration bit.
Two-Speed Start-up should be enabled only if the
primary oscillator mode is HS or HSPLL
(Crystal-Based) modes. Since the EC and ECPLL
modes do not require an OST start-up delay,
Two-Speed Start-up should be disabled.
When enabled, Resets and wake-ups from Sleep mode
cause the device to configure itself to run from the inter-
nal oscillator block as the clock source, following the
time-out of the Power-up Timer after a Power-on Reset
is enabled. This allows almost immediate code
execution while the primary oscillator starts and the
OST is running. Once the OST times out, the device
automatically switches to PRI_RUN mode.
In all other power-managed modes, Two-Speed
Start-up is not used. The device will be clocked by the
currently selected clock source until the primary clock
source becomes available. The setting of the IESO bit
is ignored.
FIGURE 26-3:
TIMING TRANSITION FOR TWO-SPEED START-UP (INTRC TO HSPLL)
Q1
Q3 Q4
OSC1
Peripheral
Program
PC
PC + 2
INTRC
PLL Clock
Q1
PC + 6
Q2
Output
Q3
Q4
Q1
CPU Clock
PC + 4
Clock
Counter
Q2
Q2
Q3
Note 1: T
OST
= 1024 T
OSC
; T
PLL
= 2 ms (approx). These intervals are not shown to scale.
Wake from Interrupt Event
T
PLL(1)
1
2
n-1 n
Clock
OSTS bit Set
Transition
T
OST(1)