Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 413
PIC18F87J72 FAMILY
FIGURE 29-10:
EXAMPLE SPI MASTER MODE TIMING (CKE = 1)
TABLE 29-15: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1)
Param.
No.
Symbol
Characteristic
Min
Max Units
Conditions
73
T
DI
V2
SC
H,
T
DI
V2
SC
L
Setup Time of SDI Data Input to SCK Edge
20
—
ns
73A
T
B
2
B
Last Clock Edge of Byte 1 to the 1st Clock Edge
of Byte 2
of Byte 2
1.5 T
CY
+ 40
—
ns
(Note 2)
74
T
SC
H2
DI
L,
T
SC
L2
DI
L
Hold Time of SDI Data Input to SCK Edge
40
—
ns
75
T
DO
R
SDO Data Output Rise Time
—
25
ns
76
T
DO
F
SDO Data Output Fall Time
—
25
ns
78
T
SC
R
SCK Output Rise Time (Master mode)
—
25
ns
79
T
SC
F
SCK Output Fall Time (Master mode)
—
25
ns
80
T
SC
H2
DO
V,
T
SC
L2
DO
V
SDO Data Output Valid after SCK Edge
—
50
ns
81
T
DO
V2
SC
H,
T
DO
V2
SC
L
SDO Data Output Setup to SCK Edge
T
CY
—
ns
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
SCK
(CKP = 0)
(CKP = 0)
SCK
(CKP = 1)
(CKP = 1)
SDO
SDI
81
74
75, 76
78
80
MSb
79
73
bit 6 - - - - - - 1
LSb In
bit 6 - - - - 1
LSb
Note:
Refer to Figure 29-3 for load conditions.
MSb In